From 4fe89f7232202040b8b8fcea2461e5ae6be2d739 Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Wed, 12 Apr 2006 03:44:45 -0400
Subject: add OSFlags struct to AlphaISA/MipsISA namespace. The OS classes then
 use these OSFlags to access architecture-specific AND OS-specific flags for
 their functions (e.g. OS::OSFlags::TG_MAP_ANONYMOUS)...

arch/alpha/tru64/process.cc:
sim/syscall_emul.hh:
    Add OSFlags to code
arch/mips/isa/decoder.isa:
    slight decoder changes (more stylistic then anything)
arch/mips/isa/formats/util.isa:
    spacing
arch/mips/isa_traits.hh:
    add OSFlags struct to MipsISA namespace. The OS classes then use these OSFlags to access architecture-specific and OS-specific
    flags for their functions
kern/linux/linux.hh:
    remove constant placement ... define OSFlags in linux.hh
kern/tru64/tru64.hh:
    define OSFlags in tru64

--HG--
extra : convert_revision : 59be1036eb439ca4ea1eea1d3b52e508023de6c9
---
 arch/mips/isa/decoder.isa      | 12 +++++++-----
 arch/mips/isa/formats/util.isa |  4 +++-
 2 files changed, 10 insertions(+), 6 deletions(-)

(limited to 'arch/mips/isa')

diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index 35e5fa75b..ffedfbca8 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -143,9 +143,11 @@ decode OPCODE_HI default Unknown::unknown() {
                     }});
 
                     0x1: multu({{
-                        int64_t temp1 = Rs.uw * Rt.uw;
-                        xc->setMiscReg(Hi,temp1<63:32>);
-                        xc->setMiscReg(Lo,temp1<31:0>);
+                        uint64_t temp1 = Rs.uw * Rt.uw;
+                        uint32_t hi_val = temp1<63:32>;
+                        uint32_t lo_val = temp1<31:0>;
+                        xc->setMiscReg(Hi,hi_val);
+                        xc->setMiscReg(Lo,lo_val);
                     }});
 
                     0x2: div({{
@@ -154,8 +156,8 @@ decode OPCODE_HI default Unknown::unknown() {
                     }});
 
                     0x3: divu({{
-                        xc->setMiscReg(Hi,Rs.uw % Rt.uw);
-                        xc->setMiscReg(Lo,Rs.uw / Rt.uw);
+                      xc->setMiscReg(Hi,Rs.uw % Rt.uw);
+                      xc->setMiscReg(Lo,Rs.uw / Rt.uw);
                     }});
                 }
             }
diff --git a/arch/mips/isa/formats/util.isa b/arch/mips/isa/formats/util.isa
index db4bf204a..dcdf46757 100644
--- a/arch/mips/isa/formats/util.isa
+++ b/arch/mips/isa/formats/util.isa
@@ -93,7 +93,9 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
 
 output exec {{
 
-using namespace MipsISA;
+    using namespace MipsISA;
+
+
 
 
     /// CLEAR ALL CPU INST/EXE HAZARDS
-- 
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