From 97429d8eeede120a2a78407f3573aa7a05075a89 Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Tue, 2 May 2006 20:05:16 -0400
Subject: Redo the FloatRegFile using unsigned integers Edit the
 convert_and_round function which access FloatRegFile

arch/isa_parser.py:
    recognize when we are writing a 'uint64_t' FloatReg and set the width appropriately
arch/mips/isa/decoder.isa:
    Send a 'float' to the convert function instead of a unsigned word. Do this so we dont have to worry about the
    bit manipulation ourselves. We can just concern ourselves with values.

    Use unsigned double to get movd...
arch/mips/isa/formats/fp.isa:
    float debug statement
arch/mips/isa_traits.cc:
    add different versions of convert_and_round functions
arch/mips/isa_traits.hh:
    Use an array of uint32_t unsigned integers to represent the Floating Point Regfile
configs/test/hello_mips:
    basic FP program
cpu/simple/cpu.hh:
    spacing

--HG--
extra : convert_revision : a6fca91ad6365c83025f1131d71fa1b8ee76d7bc
---
 arch/mips/isa/decoder.isa    | 6 +++---
 arch/mips/isa/formats/fp.isa | 2 ++
 2 files changed, 5 insertions(+), 3 deletions(-)

(limited to 'arch/mips/isa')

diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index 99ff4d737..9bafe9f34 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -397,7 +397,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     format FloatOp {
                         0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }});
                         0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
-                        0x4: mtc1 ({{ Fs.uw = Rt.uw;           }});
+                        0x4: mtc1 ({{ Fs.uw = Rt.uw;       }});
                         0x7: mthc1({{
                              uint64_t fs_hi = Rt.ud << 32;
                              uint64_t fs_lo = Fs.ud & 0x0000FFFF;
@@ -572,7 +572,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             format FloatOp {
                                 0x1: cvt_d_s({{
                                     int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                    Fd.ud = convert_and_round(Fs.uw, SINGLE_TO_DOUBLE, rnd_mode);
+                                    Fd.ud = convert_and_round(Fs.sf, SINGLE_TO_DOUBLE, rnd_mode);
                                 }});
 
                                 0x4: cvt_w_s({{
@@ -605,7 +605,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                 0x3: divd({{ Fd.df = Fs.df / Ft.df;}});
                                 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}});
                                 0x5: absd({{ Fd.df = fabs(Fs.df);}});
-                                0x6: movd({{ Fd.df = Fs.df;}});
+                                0x6: movd({{ Fd.ud = Fs.ud;}});
                                 0x7: negd({{ Fd.df = -1 * Fs.df;}});
                             }
                         }
diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa
index 65b259e20..fe6bd437f 100644
--- a/arch/mips/isa/formats/fp.isa
+++ b/arch/mips/isa/formats/fp.isa
@@ -32,6 +32,7 @@ output decoder {{
 
 // Primary format for float operate instructions:
 def format FloatOp(code, *flags) {{
+        code = 'std::cout << "Floating Point Op" << std::endl;\n' + code
         iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
@@ -41,6 +42,7 @@ def format FloatOp(code, *flags) {{
 
 // Primary format for float64 operate instructions:
 def format Float64Op(code, *flags) {{
+        code = 'std::cout << "Floating Point 64" << std::endl;\n' + code
         iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-- 
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