From 609c4ecea618c6406e50432e38882925db7b7ede Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 18 Apr 2006 09:44:24 -0400 Subject: Changed MIPS and Alpha to pass the syscall number to the syscall function arch/alpha/isa/decoder.isa: Fixed up Alpha to pass the syscall number directly to the syscall function. arch/mips/isa/decoder.isa: Fixed up MIPS to pass the syscall number directly to the syscall function. arch/mips/isa/operands.isa: Added an R2 operand which is passed to the syscall function as the syscall number to use. --HG-- extra : convert_revision : 066d486cd6a2761b29e413c6d526c268788975f3 --- arch/mips/isa/decoder.isa | 2 +- arch/mips/isa/operands.isa | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/mips/isa') diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index f5dd3d911..2df2b0403 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -89,7 +89,7 @@ decode OPCODE_HI default Unknown::unknown() { } format BasicOp { - 0x4: syscall({{ xc->syscall(); }},IsNonSpeculative); + 0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative); 0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative); 0x7: sync({{ panic("Not implemented sync yet"); }},IsNonSpeculative); } diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa index 13870337b..c01496dc9 100644 --- a/arch/mips/isa/operands.isa +++ b/arch/mips/isa/operands.isa @@ -18,6 +18,7 @@ def operands {{ 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3), 'r31': ('IntReg', 'uw','R31','IsInteger', 4), 'R0': ('IntReg', 'uw','R0', 'IsInteger', 5), + 'R2': ('IntReg', 'uw','2', 'IsInteger', 5), 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3), -- cgit v1.2.3