From b203d7bd33fd4552c556cf3cea7007d717d04375 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Wed, 8 Feb 2006 14:50:07 -0500 Subject: add at least BasicOp Format to most if not all instructions and file name changes ... arch/mips/isa/decoder.isa: add at least BasicOp Format to most if not all instructions --HG-- rename : arch/mips/isa/formats/basic.format => arch/mips/isa/formats/basic.isa rename : arch/mips/isa/formats/branch.format => arch/mips/isa/formats/branch.isa rename : arch/mips/isa/formats/fp.format => arch/mips/isa/formats/fp.isa rename : arch/mips/isa/formats/int.format => arch/mips/isa/formats/int.isa rename : arch/mips/isa/formats/mem.format => arch/mips/isa/formats/mem.isa rename : arch/mips/isa/formats/noop.format => arch/mips/isa/formats/noop.isa rename : arch/mips/isa/formats/tlbop.format => arch/mips/isa/formats/tlbop.isa rename : arch/mips/isa/formats/trap.format => arch/mips/isa/formats/trap.isa rename : arch/mips/isa/mips.isa => arch/mips/isa/main.isa extra : convert_revision : 0b2f3aee13fee3e0e25c0c746af4216c4a596391 --- arch/mips/isa/decoder.isa | 207 ++++++++++++++++++++---------------- arch/mips/isa/formats/basic.format | 65 ----------- arch/mips/isa/formats/basic.isa | 65 +++++++++++ arch/mips/isa/formats/branch.format | 66 ------------ arch/mips/isa/formats/branch.isa | 66 ++++++++++++ arch/mips/isa/formats/fp.format | 110 ------------------- arch/mips/isa/formats/fp.isa | 110 +++++++++++++++++++ arch/mips/isa/formats/int.format | 70 ------------ arch/mips/isa/formats/int.isa | 70 ++++++++++++ arch/mips/isa/formats/mem.format | 78 -------------- arch/mips/isa/formats/mem.isa | 78 ++++++++++++++ arch/mips/isa/formats/noop.format | 47 -------- arch/mips/isa/formats/noop.isa | 47 ++++++++ arch/mips/isa/formats/tlbop.format | 53 --------- arch/mips/isa/formats/tlbop.isa | 53 +++++++++ arch/mips/isa/formats/trap.format | 53 --------- arch/mips/isa/formats/trap.isa | 53 +++++++++ arch/mips/isa/main.isa | 52 +++++++++ arch/mips/isa/mips.isa | 52 --------- 19 files changed, 710 insertions(+), 685 deletions(-) delete mode 100644 arch/mips/isa/formats/basic.format create mode 100644 arch/mips/isa/formats/basic.isa delete mode 100644 arch/mips/isa/formats/branch.format create mode 100644 arch/mips/isa/formats/branch.isa delete mode 100644 arch/mips/isa/formats/fp.format create mode 100644 arch/mips/isa/formats/fp.isa delete mode 100644 arch/mips/isa/formats/int.format create mode 100644 arch/mips/isa/formats/int.isa delete mode 100644 arch/mips/isa/formats/mem.format create mode 100644 arch/mips/isa/formats/mem.isa delete mode 100644 arch/mips/isa/formats/noop.format create mode 100644 arch/mips/isa/formats/noop.isa delete mode 100644 arch/mips/isa/formats/tlbop.format create mode 100644 arch/mips/isa/formats/tlbop.isa delete mode 100644 arch/mips/isa/formats/trap.format create mode 100644 arch/mips/isa/formats/trap.isa create mode 100644 arch/mips/isa/main.isa delete mode 100644 arch/mips/isa/mips.isa (limited to 'arch/mips') diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index f0c3fc562..e29b57602 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -17,7 +17,7 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x0: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { 0x1: decode MOVCI { - format Move { + format BasicOp { 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}}); 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}}); } @@ -61,7 +61,7 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x1: jalr(IsCall,IsReturn); } - format Move { + format BasicOp { 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); } @@ -75,10 +75,10 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x2: decode FUNCTION_LO { format BasicOp { - 0x0: mfhi({{ Rd = xc->miscRegs.Hi; }}); - 0x1: mthi({{ xc->miscRegs.Hi = Rs; }}); - 0x2: mflo({{ Rd = xc->miscRegs.Lo; }}); - 0x3: mtlo({{ xc->miscRegs.Lo = Rs; }}); + 0x0: mfhi({{ Rd = xc->miscRegs.hi; }}); + 0x1: mthi({{ xc->miscRegs.hi = Rs; }}); + 0x2: mflo({{ Rd = xc->miscRegs.lo; }}); + 0x3: mtlo({{ xc->miscRegs.lo = Rs; }}); } }; @@ -86,25 +86,25 @@ decode OPCODE_HI default FailUnimpl::unknown() { format IntOp { 0x0: mult({{ INT64 temp1 = Rs.sw * Rt.sw; - xc->miscRegs.Hi->temp1<63:32>; - xc->miscRegs.Lo->temp1<31:0> + xc->miscRegs.hi->temp1<63:32>; + xc->miscRegs.lo->temp1<31:0> }}); 0x1: multu({{ INT64 temp1 = Rs.uw * Rt.uw; - xc->miscRegs.Hi->temp1<63:32>; - xc->miscRegs.Lo->temp1<31:0> + xc->miscRegs.hi->temp1<63:32>; + xc->miscRegs.lo->temp1<31:0> Rd.sw = Rs.uw * Rt.uw; }}); 0x2: div({{ - xc->miscRegs.Hi = Rs.sw % Rt.sw; - xc->miscRegs.Lo = Rs.sw / Rt.sw; + xc->miscRegs.hi = Rs.sw % Rt.sw; + xc->miscRegs.lo = Rs.sw / Rt.sw; }}); 0x3: divu({{ - xc->miscRegs.Hi = Rs.uw % Rt.uw; - xc->miscRegs.Lo = Rs.uw / Rt.uw; + xc->miscRegs.hi = Rs.uw % Rt.uw; + xc->miscRegs.lo = Rs.uw / Rt.uw; }}); } }; @@ -213,9 +213,12 @@ decode OPCODE_HI default FailUnimpl::unknown() { //Table A-11 MIPS32 COP0 Encoding of rs Field 0x0: decode RS_MSB { 0x0: decode RS { - 0x0: mfc0({{ }}); - 0xC: mtc0({{ }}); - 0xA: rdpgpr({{ }}); + + format BasicOp { + 0x0: mfc0({{ }}); + 0xC: mtc0({{ }}); + 0xA: rdpgpr({{ }}); + } 0xB: decode SC { format BasicOp { @@ -224,7 +227,7 @@ decode OPCODE_HI default FailUnimpl::unknown() { } } - 0xE: wrpgpr({{ }}); + 0xE: BasicOp::wrpgpr({{ }}); } //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO @@ -281,43 +284,49 @@ decode OPCODE_HI default FailUnimpl::unknown() { //(( single-word )) 0x0: decode RS_HI { 0x0: decode RS_LO { - 0x0: add_fmt({{ }}); - 0x1: sub_fmt({{ }}); - 0x2: mul_fmt({{ }}); - 0x3: div_fmt({{ }}); - 0x4: sqrt_fmt({{ }}); - 0x5: abs_fmt({{ }}); - 0x6: mov_fmt({{ }}); - 0x7: neg_fmt({{ }}); + format FloatOp { + 0x0: add_fmt({{ }}); + 0x1: sub_fmt({{ }}); + 0x2: mul_fmt({{ }}); + 0x3: div_fmt({{ }}); + 0x4: sqrt_fmt({{ }}); + 0x5: abs_fmt({{ }}); + 0x6: mov_fmt({{ }}); + 0x7: neg_fmt({{ }}); + } } 0x1: decode RS_LO { //only legal for 64 bit - format mode64 { + format Float64Op { 0x0: round_l({{ }}); 0x1: trunc_l({{ }}); 0x2: ceil_l({{ }}); 0x3: floor_l({{ }}); } - 0x4: round_w({{ }}); - 0x5: trunc_w({{ }}); - 0x6: ceil_w({{ }}); - 0x7: floor_w({{ }}); + format FloatOp { + 0x4: round_w({{ }}); + 0x5: trunc_w({{ }}); + 0x6: ceil_w({{ }}); + 0x7: floor_w({{ }}); + } } 0x2: decode RS_LO { 0x1: decode MOVCF { - 0x0: movf_fmt({{ }}); - 0x1: movt_fmt({{ }}); + format BasicOp { + 0x0: movf_fmt({{ }}); + 0x1: movt_fmt({{ }}); + } } - format Move { + format BasicOp { 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); } - format mode64 { + format Float64Op { 0x2: recip({{ }}); 0x3: rsqrt{{ }}); } @@ -328,7 +337,7 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x4: cvt_w({{ }}); //only legal for 64 bit - format mode64 { + format Float64Op { 0x5: cvt_l({{ }}); 0x6: cvt_ps({{ }}); } @@ -444,12 +453,14 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x2: decode RS_MSB { 0x0: decode RS_HI { 0x0: decode RS_LO { - 0x0: mfc2({{ }}); - 0x2: cfc2({{ }}); - 0x3: mfhc2({{ }}); - 0x4: mtc2({{ }}); - 0x6: ctc2({{ }}); - 0x7: mftc2({{ }}); + format WarnUnimpl { + 0x0: mfc2({{ }}); + 0x2: cfc2({{ }}); + 0x3: mfhc2({{ }}); + 0x4: mtc2({{ }}); + 0x6: ctc2({{ }}); + 0x7: mftc2({{ }}); + } } 0x1: decode ND { @@ -475,50 +486,58 @@ decode OPCODE_HI default FailUnimpl::unknown() { //operations are enabled." 0x3: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { - 0x0: lwxc1({{ }}); - 0x1: ldxc1({{ }}); - 0x5: luxc1({{ }}); + format Memory { + 0x0: lwxc1({{ }}); + 0x1: ldxc1({{ }}); + 0x5: luxc1({{ }}); + } } 0x1: decode FUNCTION_LO { - 0x0: swxc1({{ }}); - 0x1: sdxc1({{ }}); - 0x5: suxc1({{ }}); - 0x7: prefx({{ }}); + format Memory { + 0x0: swxc1({{ }}); + 0x1: sdxc1({{ }}); + 0x5: suxc1({{ }}); + 0x7: prefx({{ }}); + } } - 0x3: alnv_ps({{ }}); + format FloatOp { + 0x3: alnv_ps({{ }}); - 0x4: decode FUNCTION_LO { - 0x0: madd_s({{ }}); - 0x1: madd_d({{ }}); - 0x6: madd_ps({{ }}); - } + 0x4: decode FUNCTION_LO { + 0x0: madd_s({{ }}); + 0x1: madd_d({{ }}); + 0x6: madd_ps({{ }}); + } - 0x5: decode FUNCTION_LO { - 0x0: msub_s({{ }}); - 0x1: msub_d({{ }}); - 0x6: msub_ps({{ }}); - } + 0x5: decode FUNCTION_LO { + 0x0: msub_s({{ }}); + 0x1: msub_d({{ }}); + 0x6: msub_ps({{ }}); + } - 0x6: decode FUNCTION_LO { - 0x0: nmadd_s({{ }}); - 0x1: nmadd_d({{ }}); - 0x6: nmadd_ps({{ }}); - } + 0x6: decode FUNCTION_LO { + 0x0: nmadd_s({{ }}); + 0x1: nmadd_d({{ }}); + 0x6: nmadd_ps({{ }}); + } - 0x7: decode FUNCTION_LO { - 0x0: nmsub_s({{ }}); - 0x1: nmsub_d({{ }}); - 0x6: nmsub_ps({{ }}); + 0x7: decode FUNCTION_LO { + 0x0: nmsub_s({{ }}); + 0x1: nmsub_d({{ }}); + 0x6: nmsub_ps({{ }}); + } } } //MIPS obsolete instructions - 0x4: beql({{ cond = (Rs.sq == 0); }}); - 0x5: bnel({{ cond = (Rs.sq != 0); }}); - 0x6: blezl({{ cond = (Rs.sq <= 0); }}); - 0x7: bgtzl({{ cond = (Rs.sq > 0); }}); + format Branch { + 0x4: beql({{ cond = (Rs.sq == 0); }}); + 0x5: bnel({{ cond = (Rs.sq != 0); }}); + 0x6: blezl({{ cond = (Rs.sq <= 0); }}); + 0x7: bgtzl({{ cond = (Rs.sq > 0); }}); + } }; 0x3: decode OPCODE_LO default FailUnimpl::reserved() { @@ -531,15 +550,15 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x0: madd({{ INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; temp1 = temp1 + (Rs.sw * Rt.sw); - xc->miscRegs.Hi->temp1<63:32>; - xc->miscRegs.Lo->temp1<31:0> + xc->miscRegs.hi->temp1<63:32>; + xc->miscRegs.lo->temp1<31:0> }}); 0x1: maddu({{ INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; temp1 = temp1 + (Rs.uw * Rt.uw); - xc->miscRegs.Hi->temp1<63:32>; - xc->miscRegs.Lo->temp1<31:0> + xc->miscRegs.hi->temp1<63:32>; + xc->miscRegs.lo->temp1<31:0> }}); 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); @@ -547,26 +566,28 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x4: msub({{ INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; temp1 = temp1 - (Rs.sw * Rt.sw); - xc->miscRegs.Hi->temp1<63:32>; - xc->miscRegs.Lo->temp1<31:0> + xc->miscRegs.hi->temp1<63:32>; + xc->miscRegs.lo->temp1<31:0> }}); 0x5: msubu({{ INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; temp1 = temp1 - (Rs.uw * Rt.uw); - xc->miscRegs.Hi->temp1<63:32>; - xc->miscRegs.Lo->temp1<31:0> + xc->miscRegs.hi->temp1<63:32>; + xc->miscRegs.lo->temp1<31:0> }}); } } 0x4: decode FUNCTION_LO { - 0x0: clz({{ }}); - 0x1: clo({{ }}); + format BasicOp { + 0x0: clz({{ }}); + 0x1: clo({{ }}); + } } 0x7: decode FUNCTION_LO { - 0x7: sdbbp({{ }}); + 0x7: BasicOp::sdbbp({{ }}); } } @@ -574,19 +595,23 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x7: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { - 0x1: ext({{ }}); - 0x4: ins({{ }}); + format Branch { + 0x1: ext({{ }}); + 0x4: ins({{ }}); + } } //Table A-10 MIPS32 BSHFL Encoding of sa Field 0x4: decode SA { - 0x02: wsbh({{ }}); - 0x10: seb({{ }}); - 0x18: seh({{ }}); + format BasicOp { + 0x02: wsbh({{ }}); + 0x10: seb({{ }}); + 0x18: seh({{ }}); + } } 0x6: decode FUNCTION_LO { - 0x7: rdhwr({{ }}); + 0x7: BasicOp::rdhwr({{ }}); } } }; @@ -614,7 +639,7 @@ decode OPCODE_HI default FailUnimpl::unknown() { 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign); }; - format FailUnimpl { + format WarnUnimpl { 0x4: reserved({{ }}); 0x5: reserved({{ }}); 0x7: cache({{ }}); diff --git a/arch/mips/isa/formats/basic.format b/arch/mips/isa/formats/basic.format deleted file mode 100644 index 8fba9845a..000000000 --- a/arch/mips/isa/formats/basic.format +++ /dev/null @@ -1,65 +0,0 @@ - -// Declarations for execute() methods. -def template BasicExecDeclare {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; -}}; - -// Basic instruction class declaration template. -def template BasicDeclare {{ - /** - * Static instruction class for "%(mnemonic)s". - */ - class %(class_name)s : public %(base_class)s - { - public: - /// Constructor. - %(class_name)s(MachInst machInst); - %(BasicExecDeclare)s - }; -}}; - -// Basic instruction class constructor template. -def template BasicConstructor {{ - inline %(class_name)s::%(class_name)s(MachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) - { - %(constructor)s; - } -}}; - -// Basic instruction class execute method template. -def template BasicExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const - { - Fault fault = No_Fault; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; - %(code)s; - - if(fault == No_Fault) - { - %(op_wb)s; - } - return fault; - } -}}; - -// Basic decode template. -def template BasicDecode {{ - return new %(class_name)s(machInst); -}}; - -// Basic decode template, passing mnemonic in as string arg to constructor. -def template BasicDecodeWithMnemonic {{ - return new %(class_name)s("%(mnemonic)s", machInst); -}}; - -// The most basic instruction format... used only for a few misc. insts -def format BasicOperate(code, *flags) {{ - iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) -}}; diff --git a/arch/mips/isa/formats/basic.isa b/arch/mips/isa/formats/basic.isa new file mode 100644 index 000000000..8fba9845a --- /dev/null +++ b/arch/mips/isa/formats/basic.isa @@ -0,0 +1,65 @@ + +// Declarations for execute() methods. +def template BasicExecDeclare {{ + Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; +}}; + +// Basic instruction class declaration template. +def template BasicDeclare {{ + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + /// Constructor. + %(class_name)s(MachInst machInst); + %(BasicExecDeclare)s + }; +}}; + +// Basic instruction class constructor template. +def template BasicConstructor {{ + inline %(class_name)s::%(class_name)s(MachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + { + %(constructor)s; + } +}}; + +// Basic instruction class execute method template. +def template BasicExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + Fault fault = No_Fault; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_rd)s; + %(code)s; + + if(fault == No_Fault) + { + %(op_wb)s; + } + return fault; + } +}}; + +// Basic decode template. +def template BasicDecode {{ + return new %(class_name)s(machInst); +}}; + +// Basic decode template, passing mnemonic in as string arg to constructor. +def template BasicDecodeWithMnemonic {{ + return new %(class_name)s("%(mnemonic)s", machInst); +}}; + +// The most basic instruction format... used only for a few misc. insts +def format BasicOperate(code, *flags) {{ + iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; diff --git a/arch/mips/isa/formats/branch.format b/arch/mips/isa/formats/branch.format deleted file mode 100644 index 5327f30e8..000000000 --- a/arch/mips/isa/formats/branch.format +++ /dev/null @@ -1,66 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Branch instructions -// - -output header {{ - /** - * Base class for integer operations. - */ - class Branch : public MipsStaticInst - { - protected: - - /// Constructor - Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of integer instruction\n"; - } -}}; - -def template BranchExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const - { - //Attempt to execute the instruction - try - { - checkPriv; - - %(op_decl)s; - %(op_rd)s; - %(code)s; - } - //If we have an exception for some reason, - //deal with it - catch(MipsException except) - { - //Deal with exception - return No_Fault; - } - - //Write the resulting state to the execution context - %(op_wb)s; - - return No_Fault; - } -}}; - -// Primary format for integer operate instructions: -def format Branch(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = BranchExecute.subst(iop) -}}; diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa new file mode 100644 index 000000000..5327f30e8 --- /dev/null +++ b/arch/mips/isa/formats/branch.isa @@ -0,0 +1,66 @@ +//////////////////////////////////////////////////////////////////// +// +// Branch instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class Branch : public MipsStaticInst + { + protected: + + /// Constructor + Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template BranchExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Attempt to execute the instruction + try + { + checkPriv; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + } + //If we have an exception for some reason, + //deal with it + catch(MipsException except) + { + //Deal with exception + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Branch(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = BranchExecute.subst(iop) +}}; diff --git a/arch/mips/isa/formats/fp.format b/arch/mips/isa/formats/fp.format deleted file mode 100644 index 707109fc2..000000000 --- a/arch/mips/isa/formats/fp.format +++ /dev/null @@ -1,110 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Floating Point operate instructions -// - -output header {{ - /** - * Base class for integer operations. - */ - class FPOp : public MipsStaticInst - { - protected: - - /// Constructor - FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string FPOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of integer instruction\n"; - } -}}; - -def template FPExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const - { - //These are set to constants when the execute method - //is generated - bool useCc = ; - bool checkPriv = ; - - //Attempt to execute the instruction - try - { - checkPriv; - - %(op_decl)s; - %(op_rd)s; - %(code)s; - } - //If we have an exception for some reason, - //deal with it - catch(MipsException except) - { - //Deal with exception - return No_Fault; - } - - //Write the resulting state to the execution context - %(op_wb)s; - if(useCc) - { - xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63); - xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0); - xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue; - xc->regs.miscRegFile.ccrFields.iccFields.c = icValue; - xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31); - xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0); - xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue; - xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue; - } - return No_Fault; - } -}}; - -// Primary format for integer operate instructions: -def format FPOp(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - checkPriv = (code.find('checkPriv') != -1) - code.replace('checkPriv', '') - if checkPriv: - code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') - else: - code.replace('checkPriv;', '') - for (marker, value) in (('ivValue', '0'), ('icValue', '0'), - ('xvValue', '0'), ('xcValue', '0')): - code.replace(marker, value) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = IntegerExecute.subst(iop) -}}; - -// Primary format for integer operate instructions: -def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - checkPriv = (code.find('checkPriv') != -1) - code.replace('checkPriv', '') - if checkPriv: - code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') - else: - code.replace('checkPriv;', '') - for (marker, value) in (('ivValue', ivValue), ('icValue', icValue), - ('xvValue', xvValue), ('xcValue', xcValue)): - code.replace(marker, value) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = IntegerExecute.subst(iop) -}}; diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa new file mode 100644 index 000000000..707109fc2 --- /dev/null +++ b/arch/mips/isa/formats/fp.isa @@ -0,0 +1,110 @@ +//////////////////////////////////////////////////////////////////// +// +// Floating Point operate instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class FPOp : public MipsStaticInst + { + protected: + + /// Constructor + FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string FPOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template FPExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //These are set to constants when the execute method + //is generated + bool useCc = ; + bool checkPriv = ; + + //Attempt to execute the instruction + try + { + checkPriv; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + } + //If we have an exception for some reason, + //deal with it + catch(MipsException except) + { + //Deal with exception + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + if(useCc) + { + xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63); + xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0); + xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue; + xc->regs.miscRegFile.ccrFields.iccFields.c = icValue; + xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31); + xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0); + xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue; + xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue; + } + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format FPOp(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + checkPriv = (code.find('checkPriv') != -1) + code.replace('checkPriv', '') + if checkPriv: + code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') + else: + code.replace('checkPriv;', '') + for (marker, value) in (('ivValue', '0'), ('icValue', '0'), + ('xvValue', '0'), ('xcValue', '0')): + code.replace(marker, value) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = IntegerExecute.subst(iop) +}}; + +// Primary format for integer operate instructions: +def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + checkPriv = (code.find('checkPriv') != -1) + code.replace('checkPriv', '') + if checkPriv: + code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') + else: + code.replace('checkPriv;', '') + for (marker, value) in (('ivValue', ivValue), ('icValue', icValue), + ('xvValue', xvValue), ('xcValue', xcValue)): + code.replace(marker, value) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = IntegerExecute.subst(iop) +}}; diff --git a/arch/mips/isa/formats/int.format b/arch/mips/isa/formats/int.format deleted file mode 100644 index 5b8df54e9..000000000 --- a/arch/mips/isa/formats/int.format +++ /dev/null @@ -1,70 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Integer operate instructions -// - -output header {{ - /** - * Base class for integer operations. - */ - class IntOp : public MipsStaticInst - { - protected: - - /// Constructor - IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; - - class IntImmOp : public MipsStaticInst - { - protected: - uint16_t imm; - - /// Constructor - IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : - MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; - -}}; - -output decoder {{ - std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of integer instruction\n"; - } - - std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of integer immediate instruction\n"; - } -}}; - -// Primary format for integer operate instructions: -def format IntOp(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - - //Figure out if we are creating a IntImmOp or a IntOp - strlen = len(name) - if ( name[strlen-1] = 'i' or ( name[strlen-2:] = 'iu')) - iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags) - else: - iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags) - - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = OperateNopCheckDecode.subst(iop) - exec_output = BasicExecute.subst(iop) -}}; - - - diff --git a/arch/mips/isa/formats/int.isa b/arch/mips/isa/formats/int.isa new file mode 100644 index 000000000..5b8df54e9 --- /dev/null +++ b/arch/mips/isa/formats/int.isa @@ -0,0 +1,70 @@ +//////////////////////////////////////////////////////////////////// +// +// Integer operate instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class IntOp : public MipsStaticInst + { + protected: + + /// Constructor + IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; + + class IntImmOp : public MipsStaticInst + { + protected: + uint16_t imm; + + /// Constructor + IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : + MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; + +}}; + +output decoder {{ + std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } + + std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer immediate instruction\n"; + } +}}; + +// Primary format for integer operate instructions: +def format IntOp(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + + //Figure out if we are creating a IntImmOp or a IntOp + strlen = len(name) + if ( name[strlen-1] = 'i' or ( name[strlen-2:] = 'iu')) + iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags) + else: + iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags) + + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = OperateNopCheckDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; + + + diff --git a/arch/mips/isa/formats/mem.format b/arch/mips/isa/formats/mem.format deleted file mode 100644 index 5ed5237c5..000000000 --- a/arch/mips/isa/formats/mem.format +++ /dev/null @@ -1,78 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Mem instructions -// - -output header {{ - /** - * Base class for integer operations. - */ - class Mem : public MipsStaticInst - { - protected: - - /// Constructor - Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of integer instruction\n"; - } -}}; - -def template MemExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const - { - //Attempt to execute the instruction - try - { - - %(op_decl)s; - %(op_rd)s; - ea_code - %(code)s; - } - //If we have an exception for some reason, - //deal with it - catch(MipsException except) - { - //Deal with exception - return No_Fault; - } - - //Write the resulting state to the execution context - %(op_wb)s; - - return No_Fault; - } -}}; - -// Primary format for integer operate instructions: -def format Mem(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = MemExecute.subst(iop) - exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;'); -}}; - -def format Cas(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = MemExecute.subst(iop) - exec_output.replace('ea_code', 'EA = R1;'); -}}; diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa new file mode 100644 index 000000000..5ed5237c5 --- /dev/null +++ b/arch/mips/isa/formats/mem.isa @@ -0,0 +1,78 @@ +//////////////////////////////////////////////////////////////////// +// +// Mem instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class Mem : public MipsStaticInst + { + protected: + + /// Constructor + Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template MemExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Attempt to execute the instruction + try + { + + %(op_decl)s; + %(op_rd)s; + ea_code + %(code)s; + } + //If we have an exception for some reason, + //deal with it + catch(MipsException except) + { + //Deal with exception + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Mem(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = MemExecute.subst(iop) + exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;'); +}}; + +def format Cas(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = MemExecute.subst(iop) + exec_output.replace('ea_code', 'EA = R1;'); +}}; diff --git a/arch/mips/isa/formats/noop.format b/arch/mips/isa/formats/noop.format deleted file mode 100644 index b1ece654d..000000000 --- a/arch/mips/isa/formats/noop.format +++ /dev/null @@ -1,47 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Noop instruction -// - -output header {{ - /** - * Base class for integer operations. - */ - class Noop : public MipsStaticInst - { - protected: - - /// Constructor - Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string Noop::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of integer instruction\n"; - } -}}; - -def template NoopExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const - { - //Nothing to see here, move along - return No_Fault; - } -}}; - -// Primary format for integer operate instructions: -def format Noop(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = NoopExecute.subst(iop) -}}; diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa new file mode 100644 index 000000000..b1ece654d --- /dev/null +++ b/arch/mips/isa/formats/noop.isa @@ -0,0 +1,47 @@ +//////////////////////////////////////////////////////////////////// +// +// Noop instruction +// + +output header {{ + /** + * Base class for integer operations. + */ + class Noop : public MipsStaticInst + { + protected: + + /// Constructor + Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Noop::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template NoopExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Nothing to see here, move along + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Noop(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = NoopExecute.subst(iop) +}}; diff --git a/arch/mips/isa/formats/tlbop.format b/arch/mips/isa/formats/tlbop.format deleted file mode 100644 index f5e4076f2..000000000 --- a/arch/mips/isa/formats/tlbop.format +++ /dev/null @@ -1,53 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// TlbOp instructions -// - -output header {{ - /** - * Base class for integer operations. - */ - class TlbOp : public MipsStaticInst - { - protected: - - /// Constructor - TlbOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string TlbOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of integer instruction\n"; - } -}}; - -def template TlbOpExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const - { - //Call into the trap handler with the appropriate fault - return No_Fault; - } - - //Write the resulting state to the execution context - %(op_wb)s; - - return No_Fault; - } -}}; - -// Primary format for integer operate instructions: -def format TlbOp(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = TlbOpExecute.subst(iop) -}}; diff --git a/arch/mips/isa/formats/tlbop.isa b/arch/mips/isa/formats/tlbop.isa new file mode 100644 index 000000000..f5e4076f2 --- /dev/null +++ b/arch/mips/isa/formats/tlbop.isa @@ -0,0 +1,53 @@ +//////////////////////////////////////////////////////////////////// +// +// TlbOp instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class TlbOp : public MipsStaticInst + { + protected: + + /// Constructor + TlbOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string TlbOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template TlbOpExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Call into the trap handler with the appropriate fault + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format TlbOp(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = TlbOpExecute.subst(iop) +}}; diff --git a/arch/mips/isa/formats/trap.format b/arch/mips/isa/formats/trap.format deleted file mode 100644 index 78f8d87b0..000000000 --- a/arch/mips/isa/formats/trap.format +++ /dev/null @@ -1,53 +0,0 @@ -//////////////////////////////////////////////////////////////////// -// -// Trap instructions -// - -output header {{ - /** - * Base class for integer operations. - */ - class Trap : public MipsStaticInst - { - protected: - - /// Constructor - Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return "Disassembly of integer instruction\n"; - } -}}; - -def template TrapExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const - { - //Call into the trap handler with the appropriate fault - return No_Fault; - } - - //Write the resulting state to the execution context - %(op_wb)s; - - return No_Fault; - } -}}; - -// Primary format for integer operate instructions: -def format Trap(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = TrapExecute.subst(iop) -}}; diff --git a/arch/mips/isa/formats/trap.isa b/arch/mips/isa/formats/trap.isa new file mode 100644 index 000000000..78f8d87b0 --- /dev/null +++ b/arch/mips/isa/formats/trap.isa @@ -0,0 +1,53 @@ +//////////////////////////////////////////////////////////////////// +// +// Trap instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class Trap : public MipsStaticInst + { + protected: + + /// Constructor + Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template TrapExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Call into the trap handler with the appropriate fault + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Trap(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = TrapExecute.subst(iop) +}}; diff --git a/arch/mips/isa/main.isa b/arch/mips/isa/main.isa new file mode 100644 index 000000000..a8c71872b --- /dev/null +++ b/arch/mips/isa/main.isa @@ -0,0 +1,52 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2003-2005 The Regents of The University of Michigan +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +##include "m5/arch/sparc/isa_desc/includes.h" + +//////////////////////////////////////////////////////////////////// +// +// Namespace statement. Everything below this line will be in the +// MipsISAInst namespace. +// + +namespace MipsISA; + +//Include the bitfield definitions +##include "m5/arch/mips/isa_desc/bitfields.h" + +//Include the operand_types and operand definitions +##include "m5/arch/mips/isa_desc/operands.h" + +//Include the base class for mips instructions, and some support code +##include "m5/arch/mips/isa_desc/base.h" + +//Include the definitions for the instruction formats +##include "m5/arch/mips/isa_desc/formats.h" + +//Include the decoder definition +##include "m5/arch/mips/isa_desc/decoder.h" diff --git a/arch/mips/isa/mips.isa b/arch/mips/isa/mips.isa deleted file mode 100644 index a8c71872b..000000000 --- a/arch/mips/isa/mips.isa +++ /dev/null @@ -1,52 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2003-2005 The Regents of The University of Michigan -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -##include "m5/arch/sparc/isa_desc/includes.h" - -//////////////////////////////////////////////////////////////////// -// -// Namespace statement. Everything below this line will be in the -// MipsISAInst namespace. -// - -namespace MipsISA; - -//Include the bitfield definitions -##include "m5/arch/mips/isa_desc/bitfields.h" - -//Include the operand_types and operand definitions -##include "m5/arch/mips/isa_desc/operands.h" - -//Include the base class for mips instructions, and some support code -##include "m5/arch/mips/isa_desc/base.h" - -//Include the definitions for the instruction formats -##include "m5/arch/mips/isa_desc/formats.h" - -//Include the decoder definition -##include "m5/arch/mips/isa_desc/decoder.h" -- cgit v1.2.3