From bd175809286e8da64176da977aeb27fc6ff6d272 Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Sat, 18 Feb 2006 14:38:23 -0500
Subject: changes from mergedmem

arch/mips/isa/formats/branch.isa:
    add branch_likely member functions
cpu/base.hh:
cpu/exec_context.hh:
cpu/static_inst.hh:
    change from mergedmem

--HG--
extra : convert_revision : d6ad6943e2ef09eac91a466fc5c9bd8e66bf319a
---
 arch/mips/isa/formats/branch.isa | 57 ++++++++++++++++++++++++++++++++++------
 1 file changed, 49 insertions(+), 8 deletions(-)

(limited to 'arch/mips')

diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa
index c003cb63d..d9dd433e3 100644
--- a/arch/mips/isa/formats/branch.isa
+++ b/arch/mips/isa/formats/branch.isa
@@ -115,6 +115,12 @@ output decoder {{
         return branchPC + 4 + disp;
     }
 
+    Addr
+    BranchLikely::branchTarget(Addr branchPC) const
+    {
+        return branchPC + 4 + disp;
+    }
+
     Addr
     Jump::branchTarget(ExecContext *xc) const
     {
@@ -162,6 +168,44 @@ output decoder {{
             ss << ",";
         }
 
+#ifdef SS_COMPATIBLE_DISASSEMBLY
+        if (_numSrcRegs == 0 && _numDestRegs == 0) {
+            printReg(ss, 31);
+            ss << ",";
+        }
+#endif
+
+        Addr target = pc + 4 + disp;
+
+        std::string str;
+        if (symtab && symtab->findSymbol(target, str))
+            ss << str;
+        else
+            ccprintf(ss, "0x%x", target);
+
+        return ss.str();
+    }
+
+    std::string
+    BranchLikely::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+
+        ccprintf(ss, "%-10s ", mnemonic);
+
+        // There's only one register arg (RA), but it could be
+        // either a source (the condition for conditional
+        // branches) or a destination (the link reg for
+        // unconditional branches)
+        if (_numSrcRegs > 0) {
+            printReg(ss, _srcRegIdx[0]);
+            ss << ",";
+        }
+        else if (_numDestRegs > 0) {
+            printReg(ss, _destRegIdx[0]);
+            ss << ",";
+        }
+
 #ifdef SS_COMPATIBLE_DISASSEMBLY
         if (_numSrcRegs == 0 && _numDestRegs == 0) {
             printReg(ss, 31);
@@ -205,16 +249,10 @@ output decoder {{
     }
 }};
 
-
-def template JumpOrBranchDecode {{
-    return (RD == 0)
-        ? (StaticInst<MipsISA> *)new %(class_name)s(machInst)
-        : (StaticInst<MipsISA> *)new %(class_name)sAndLink(machInst);
-}};
-
 def format Branch(code,*flags) {{
     code = 'bool cond;\n\t' + code + '\n'
 
+    #Add Link Code if Link instruction
     strlen = len(name)
     if name[strlen-2:] == 'al':
         code += 'R31 = NPC + 8;\n'
@@ -230,12 +268,15 @@ def format Branch(code,*flags) {{
 }};
 
 def format BranchLikely(code,*flags) {{
-    code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
+    code = 'bool cond;\n\t\t\t' + code
 
+    #Add Link Code if Link instruction
     strlen = len(name)
     if name[strlen-3:] == 'all':
         code += 'R31 = NPC + 8;\n'
 
+    code = '\t\t\tif (cond) NPC = NPC + disp;\n';
+
     iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
                         ('IsDirectControl', 'IsCondControl','IsCondDelaySlot'))
     header_output = BasicDeclare.subst(iop)
-- 
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