From 5c79eb04104e6e3dd2fd957c071fef3ceb47b722 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 31 Mar 2006 20:31:53 -0500
Subject: Fixes to SPARC for syscall emulation mode.
arch/sparc/isa/base.isa:
arch/sparc/isa/decoder.isa:
arch/sparc/isa/formats.isa:
arch/sparc/isa/formats/branch.isa:
arch/sparc/isa/formats/integerop.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/nop.isa:
arch/sparc/isa/formats/trap.isa:
arch/sparc/isa/formats/unknown.isa:
arch/sparc/isa/includes.isa:
arch/sparc/isa/operands.isa:
Fixes towards running in syscall emulation mode.
arch/sparc/linux/process.cc:
Fixed the assert and comment to check that the Num_Syscall_Descs is less than or equal to 284. Why does this assert need to exist anyway?
base/loader/elf_object.cc:
Cleared out comments about resolved issues.
cpu/simple/cpu.cc:
Use NNPC for both SPARC and MIPS, instead of just MIPS
configs/test/hello_sparc:
A test program for SPARC which prints "Hello World!"
--HG--
rename : arch/sparc/isa/formats/noop.isa => arch/sparc/isa/formats/nop.isa
extra : convert_revision : 10b3e3b9f21c215d809cffa930448007102ba698
---
arch/sparc/isa/formats/integerop.isa | 291 +++++++++++++++++++++++++++--------
1 file changed, 226 insertions(+), 65 deletions(-)
(limited to 'arch/sparc/isa/formats/integerop.isa')
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
index e7bd4c2a4..2c2123f86 100644
--- a/arch/sparc/isa/formats/integerop.isa
+++ b/arch/sparc/isa/formats/integerop.isa
@@ -11,103 +11,230 @@ output header {{
{
protected:
// Constructor
- IntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+ IntOp(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
+
+ virtual bool printPseudoOps(std::ostream &os, Addr pc,
+ const SymbolTable *symtab) const;
};
/**
- * Base class for 10 bit immediate integer operations.
+ * Base class for immediate integer operations.
*/
- class IntOpImm10 : public IntOp
+ class IntOpImm : public IntOp
{
protected:
// Constructor
- IntOpImm10(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- IntOp(mnem, _machInst, __opClass), imm(SIMM10)
+ IntOpImm(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
+ IntOp(mnem, _machInst, __opClass)
{
}
uint32_t imm;
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ virtual bool printPseudoOps(std::ostream &os, Addr pc,
+ const SymbolTable *symtab) const;
+ };
+
+ /**
+ * Base class for 10 bit immediate integer operations.
+ */
+ class IntOpImm10 : public IntOpImm
+ {
+ protected:
+ // Constructor
+ IntOpImm10(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
+ IntOpImm(mnem, _machInst, __opClass)
+ {
+ imm = SIMM10;
+ }
};
/**
* Base class for 13 bit immediate integer operations.
*/
- class IntOpImm13 : public IntOp
+ class IntOpImm13 : public IntOpImm
{
protected:
// Constructor
- IntOpImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- IntOp(mnem, _machInst, __opClass), imm(SIMM13)
+ IntOpImm13(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
+ IntOpImm(mnem, _machInst, __opClass)
{
+ imm = SIMM13;
}
+ };
- uint32_t imm;
+ /**
+ * Base class for sethi.
+ */
+ class SetHi : public IntOpImm
+ {
+ protected:
+ // Constructor
+ SetHi(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
+ IntOpImm(mnem, _machInst, __opClass)
+ {
+ imm = (IMM22 << 10) & 0xFFFFFC00;
+ }
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
};
}};
+def template SetHiDecode {{
+ {
+ if(RD == 0 && IMM22 == 0)
+ return (SparcStaticInst *)(new Nop("nop", machInst, No_OpClass));
+ else
+ return (SparcStaticInst *)(new %(class_name)s(machInst));
+ }
+}};
+
output decoder {{
- std::string IntOp::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
+
+ bool IntOp::printPseudoOps(std::ostream &os, Addr pc,
+ const SymbolTable *symbab) const
{
- return "Integer instruction\n";
+ if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
+ {
+ printMnemonic(os, "mov");
+ if(_numSrcRegs > 0)
+ printReg(os, _srcRegIdx[1]);
+ ccprintf(os, ", ");
+ if(_numDestRegs > 0)
+ printReg(os, _destRegIdx[0]);
+
+ return true;
+ }
+ return false;
}
-}};
-def template IntOpExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
+ bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
+ const SymbolTable *symbab) const
{
- Fault fault = NoFault;
+ if(!strcmp(mnemonic, "or"))
+ {
+ if(_srcRegIdx[0] == 0)
+ {
+ if(imm == 0)
+ {
+ printMnemonic(os, "clr");
+ if(_numDestRegs > 0)
+ printReg(os, _destRegIdx[0]);
+ return true;
+ }
+ else
+ {
+ printMnemonic(os, "mov");
+ ccprintf(os, ", 0x%x, ", imm);
+ if(_numDestRegs > 0)
+ printReg(os, _destRegIdx[0]);
+ return true;
+ }
+ }
+ else if(imm == 0)
+ {
+ printMnemonic(os, "mov");
+ if(_numSrcRegs > 0)
+ printReg(os, _srcRegIdx[0]);
+ ccprintf(os, ", ");
+ if(_numDestRegs > 0)
+ printReg(os, _destRegIdx[0]);
+ return true;
+ }
+ }
+ return false;
+ }
- %(op_decl)s;
- %(op_rd)s;
- %(code)s;
+ std::string IntOp::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
- //Write the resulting state to the execution context
- if(fault == NoFault)
- %(op_wb)s;
- return fault;
+ if(!printPseudoOps(response, pc, symtab))
+ {
+ printMnemonic(response, mnemonic);
+ if (_numSrcRegs > 0)
+ {
+ printReg(response, _srcRegIdx[0]);
+ for(int x = 1; x < _numSrcRegs; x++)
+ {
+ response << ", ";
+ printReg(response, _srcRegIdx[x]);
+ }
+ }
+ if (_numDestRegs > 0)
+ {
+ if(_numSrcRegs > 0)
+ response << ", ";
+ printReg(response, _destRegIdx[0]);
+ }
+ }
+ return response.str();
}
-}};
-def template IntOpCcExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
+ std::string IntOpImm::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
{
- Fault fault;
-
- %(op_decl)s;
- %(op_rd)s;
- %(code)s;
+ std::stringstream response;
- //Write the resulting state to the execution context
- if(fault == NoFault)
+ if(!printPseudoOps(response, pc, symtab))
{
- %(op_wb)s;
- CcrIccN = Rd & (1 << 63);
- CcrIccZ = (Rd == 0);
- CcrIccV = ivValue;
- CcrIccC = icValue;
- CcrXccN = Rd & (1 << 31);
- CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
- CcrXccV = xvValue;
- CcrXccC = xcValue;
+ printMnemonic(response, mnemonic);
+ if (_numSrcRegs > 1)
+ {
+ printReg(response, _srcRegIdx[0]);
+ for(int x = 1; x < _numSrcRegs - 1; x++)
+ {
+ response << ", ";
+ printReg(response, _srcRegIdx[x]);
+ }
+ }
+ if(_numSrcRegs > 0)
+ response << ", ";
+ ccprintf(response, "0x%x", imm);
+ if (_numDestRegs > 0)
+ {
+ response << ", ";
+ printReg(response, _destRegIdx[0]);
+ }
}
- return fault;
+ return response.str();
+ }
+
+ std::string SetHi::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+
+ printMnemonic(response, mnemonic);
+ if(_numSrcRegs > 0)
+ response << ", ";
+ ccprintf(response, "%%hi(0x%x), ", imm);
+ printReg(response, _destRegIdx[0]);
+ return response.str();
}
}};
-def template IntOpCcResExecute {{
+def template IntOpExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Fault fault;
+ Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
@@ -117,49 +244,83 @@ def template IntOpCcResExecute {{
if(fault == NoFault)
{
%(op_wb)s;
- CcrIccN = Rd & (1 << 63);
- CcrIccZ = (Rd == 0);
- CcrXccN = Rd & (1 << 31);
- CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
- CcrIccV = CcrIccC = CcrXccV = CcrXccC = 0;
+ %(cc_code)s;
}
return fault;
}
}};
let {{
- def doIntFormat(code, execTemplate, name, Name, opt_flags):
- (usesImm, cblk, immCblk, rString, iString) = splitOutImm(code)
- iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
+ def doIntFormat(code, ccCode, name, Name, opt_flags):
+ (usesImm, code, immCode,
+ rString, iString) = splitOutImm(code)
+ iop = genCompositeIop(code, name, Name,
+ 'IntOp', opt_flags, cc_code=ccCode)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
- exec_output = execTemplate.subst(iop)
+ exec_output = IntOpExecute.subst(iop)
if usesImm:
- imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString,
- immCblk, opt_flags)
+ imm_iop = genCompositeIop(code, name, Name + 'Imm',
+ 'IntOpImm' + iString, opt_flags, cc_code=ccCode)
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
- exec_output += execTemplate.subst(imm_iop)
+ exec_output += IntOpExecute.subst(imm_iop)
decode_block = ROrImmDecode.subst(iop)
else:
decode_block = BasicDecode.subst(iop)
+ return (header_output, decoder_output, exec_output, decode_block)
+
+ calcCcCode = '''
+ CcrIccN = (Rd >> 63) & 1;
+ CcrIccZ = (Rd == 0);
+ CcrXccN = (Rd >> 31) & 1;
+ CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
+ CcrIccV = %(ivValue)s;
+ CcrIccC = %(icValue)s;
+ CcrXccV = %(xvValue)s;
+ CcrXccC = %(xcValue)s;
+ '''
}};
// Primary format for integer operate instructions:
def format IntOp(code, *opt_flags) {{
- doIntFormat(code, IntOpExecute, name, Name, opt_flags)
+ ccCode = ''
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doIntFormat(code, ccCode,
+ name, Name, opt_flags)
}};
// Primary format for integer operate instructions:
def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
- for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
- ('xvValue', xvValue), ('xcValue', xcValue)):
- code.replace(marker, value)
- doIntFormat(code, IntOpCcExecute, name, Name, opt_flags)
+ ccCode = calcCcCode % vars()
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doIntFormat(code, ccCode,
+ name, Name, opt_flags)
}};
// Primary format for integer operate instructions:
def format IntOpCcRes(code, *opt_flags) {{
- doIntFormat(code, IntOpCcResExecute, name, Name, opt_flags)
+ ccCode = calcCcCode % {"icValue":"0",
+ "ivValue":"0",
+ "xcValue":"0",
+ "xvValue":"0"}
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doIntFormat(code, ccCode,
+ name, Name, opt_flags)
+}};
+
+def format SetHi(code, *opt_flags) {{
+ iop = genCompositeIop(code, name, Name, 'SetHi',
+ opt_flags, cc_code='')
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ exec_output = IntOpExecute.subst(iop)
+ decode_block = SetHiDecode.subst(iop)
}};
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