From a8fbc4ec76169a6d735817df2aa8bc2085df5ac8 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 30 Apr 2006 01:46:00 -0400
Subject: Got hello world to work!
arch/sparc/isa/decoder.isa:
Made sure if a register was assigned to along some control path, then all paths on which no exception would block commit set a value as well. Also, Rs1 is treated as signed for bpr instructions.
arch/sparc/isa/formats/integerop.isa:
Added an IntOpImm11 class which sign extends the SIMM11 immediate field.
arch/sparc/isa/formats/mem.isa:
Fixed how offsets are used, and how disassembly is generated.
arch/sparc/linux/process.cc:
Added fstat and exit_group syscalls.
--HG--
extra : convert_revision : 3b4427d239d254a92179a4137441125b8a364264
---
arch/sparc/isa/formats/mem.isa | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
(limited to 'arch/sparc/isa/formats/mem.isa')
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
index ab8b85a94..12dae57e5 100644
--- a/arch/sparc/isa/formats/mem.isa
+++ b/arch/sparc/isa/formats/mem.isa
@@ -30,8 +30,9 @@ output header {{
// Constructor
MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- Mem(mnem, _machInst, __opClass), imm(SIMM13)
+ Mem(mnem, _machInst, __opClass)
{
+ imm = sign_ext(SIMM13, 13);
}
std::string generateDisassembly(Addr pc,
@@ -84,7 +85,10 @@ output decoder {{
}
ccprintf(response, "[ ");
printReg(response, _srcRegIdx[!save ? 0 : 1]);
- ccprintf(response, " + 0x%x ]", imm);
+ if(imm >= 0)
+ ccprintf(response, " + 0x%x ]", imm);
+ else
+ ccprintf(response, " + -0x%x ]", -imm);
if(load)
{
ccprintf(response, ", ");
@@ -127,7 +131,7 @@ let {{
def doMemFormat(code, load, store, name, Name, opt_flags):
addrCalcReg = 'EA = Rs1 + Rs2;'
- addrCalcImm = 'EA = Rs1 + SIMM13;'
+ addrCalcImm = 'EA = Rs1 + imm;'
iop = InstObjParams(name, Name, 'Mem', code,
opt_flags, ("ea_code", addrCalcReg),
("load", load), ("store", store))
--
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