From f58d85128dde9aebb5b161aa51799309d5c16d67 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 14 Jan 2005 18:34:56 -0500 Subject: Fixes so m5 compiles on gcc 3.4, which has much stricter syntax. Most changes come from templated code, which is evaluated slightly differently than in previous versions of gcc. arch/alpha/alpha_linux_process.cc: Alphabetize includes. arch/alpha/vptr.hh: Change the constants that are being used for alpha pagebytes to come from the ISA. base/random.hh: cpu/static_inst.cc: sim/param.cc: Fix up template syntax. base/range.hh: Include iostream for << operator. base/res_list.hh: base/statistics.hh: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.hh: sim/eventq.hh: sim/param.hh: Fixup for templated code to resolve different scope lookup in gcc 3.4. This defers the lookup of the function/variable until actual instantiation time by making it dependent on the templated class/function. base/trace.cc: Fix call to new. base/trace.hh: Fix up #define to have full path. cpu/base_cpu.cc: Fix up call to new. dev/etherlink.hh: dev/ns_gige.hh: dev/sinic.hh: Fixup for friend class/function declaration. g++ 3.4 no longer allows typedefs to be declared as a friend class. dev/pcidev.hh: Fix up re-definition of access level to params. kern/linux/linux_syscalls.hh: kern/tru64/tru64_syscalls.hh: Fix up header. Fix up template syntax. sim/serialize.cc: Include errno.h. sim/startup.cc: Change startupq. queue was getting destructed before all things had called ~StartupCallback(), which lead to a segfault. This puts startupq in global space, and we allocate it ourselves. Other code may be similar to this and may need changing in the future. sim/syscall_emul.hh: Include cpu/exec_context.hh and sim/process.hh, as forward declarations are no longer sufficient. sim/universe.cc: Include errno.h --HG-- extra : convert_revision : e49d08ee89eb06a28351f02bafc028ca6652d5af --- arch/alpha/alpha_linux_process.cc | 16 ++++++++-------- arch/alpha/vptr.hh | 11 ++++++----- 2 files changed, 14 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/alpha_linux_process.cc index 67bb0ab3b..ba4b1d07e 100644 --- a/arch/alpha/alpha_linux_process.cc +++ b/arch/alpha/alpha_linux_process.cc @@ -26,24 +26,24 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include #include -#include #include // for host open() flags -#include -#include #include // for memset() -#include +#include +#include +#include -#include "sim/host.hh" #include "cpu/base_cpu.hh" -#include "mem/functional_mem/functional_memory.hh" -#include "sim/process.hh" #include "cpu/exec_context.hh" +#include "mem/functional_mem/functional_memory.hh" #include "sim/fake_syscall.hh" +#include "sim/host.hh" +#include "sim/process.hh" #include "sim/sim_events.hh" -#include "sim/syscall_emul.hh" #include "arch/alpha/alpha_common_syscall_emul.hh" +#include "sim/syscall_emul.hh" #include "sim/universe.hh" // for curTick & ticksPerSecond #include "arch/alpha/alpha_linux_process.hh" diff --git a/arch/alpha/vptr.hh b/arch/alpha/vptr.hh index cd4bc547b..e955c67cf 100644 --- a/arch/alpha/vptr.hh +++ b/arch/alpha/vptr.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __VPTR_HH__ -#define __VPTR_HH__ +#ifndef __ARCH_ALPHA_VPTR_HH__ +#define __ARCH_ALPHA_VPTR_HH__ #include "arch/alpha/vtophys.hh" @@ -69,14 +69,15 @@ class VPtr const VPtr &operator+=(int offset) { ptr += offset; - assert((ptr & (ALPHA_PGBYTES - 1)) + sizeof(T) < ALPHA_PGBYTES); + assert((ptr & (AlphaISA::PageBytes - 1)) + sizeof(T) + < AlphaISA::PageBytes); return *this; } const VPtr &operator=(Addr p) { - assert((p & (ALPHA_PGBYTES - 1)) + sizeof(T) < ALPHA_PGBYTES); + assert((p & (AlphaISA::PageBytes)) + sizeof(T) < AlphaISA::PageBytes); ptr = p; return *this; @@ -110,4 +111,4 @@ class VPtr } }; -#endif // __VPTR_HH__ +#endif // __ARCH_ALPHA_VPTR_HH__ -- cgit v1.2.3 From 6cbce7631ad7f51d98cb68bd096594bc90baffdf Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 21 Jan 2005 04:34:01 -0500 Subject: Add a couple statistics contexts. arch/alpha/pseudo_inst.cc: rename the context for consistency. sim/pyconfig/m5config.py: Add a ParamContext class so that param contexts work with the new config stuff. --HG-- extra : convert_revision : 3a6b583a25c86237baca7a2b4eccc9d12f86a384 --- arch/alpha/pseudo_inst.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/alpha/pseudo_inst.cc b/arch/alpha/pseudo_inst.cc index 95c85b45a..22d65638b 100644 --- a/arch/alpha/pseudo_inst.cc +++ b/arch/alpha/pseudo_inst.cc @@ -206,7 +206,7 @@ namespace AlphaPseudo void checkParams(); }; - Context context("PseudoInsts"); + Context context("pseudo_inst"); Param __quiesce(&context, "quiesce", "enable quiesce instructions", -- cgit v1.2.3 From 0aaf8ec6b83c65a60932fd9f9f4b81eca1bcce74 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 3 Feb 2005 20:47:11 -0500 Subject: Add support for CPU models to execute the effective address calculation and memory access portions separately. Not currently used by any CPU models, but Kevin says he needs this. Also clean up handling of execution tracing for memory accesses (move it all into isa_desc and out of CPU models). Got rid of some ancient unused code too. arch/alpha/isa_desc: Add execute() methods to EAComp and MemAcc portions of memory access instructions, to allow CPU models to execute the effective address calculation and memory access portions separately. Requires the execution context to remember the effective address across the two invocations. Added setEA() and getEA() methods to execution context to support this. A model that does not use the split execution model can panic if these methods are called. Also added hook to call traceData->setAddr() after EA computation on any load or store operation. arch/isa_parser.py: Call traceData->setData() on memory writes (stores). cpu/simple_cpu/simple_cpu.cc: Get rid of unused code. cpu/simple_cpu/simple_cpu.hh: Add (non-functional) setEA() and getEA() methods for new split memory access execution support. --HG-- extra : convert_revision : bc2d2c758c4ca753812b9fa81f21038e55929ff0 --- arch/alpha/isa_desc | 171 +++++++++++++++++++++++++++++++--------------------- arch/isa_parser.py | 6 +- 2 files changed, 107 insertions(+), 70 deletions(-) (limited to 'arch') diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 5154d78d1..5602a6ba6 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -790,48 +790,14 @@ output header {{ protected: /// Constructor MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass, - StaticInstPtr _eaCompPtr, - StaticInstPtr _memAccPtr) + StaticInstPtr _eaCompPtr = nullStaticInstPtr, + StaticInstPtr _memAccPtr = nullStaticInstPtr) : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr) { } std::string generateDisassembly(Addr pc, const SymbolTable *symtab); }; - - - /** - * Base class for "fake" effective-address computation - * instructions returnded by eaCompInst(). - */ - class EACompBase : public AlphaStaticInst - { - public: - /// Constructor - EACompBase(MachInst machInst) - : AlphaStaticInst("(eacomp)", machInst, IntAluOp) - { - } - - %(BasicExecDeclare)s - }; - - /** - * Base class for "fake" memory-access instructions returnded by - * memAccInst(). - */ - class MemAccBase : public AlphaStaticInst - { - public: - /// Constructor - MemAccBase(MachInst machInst, OpClass __opClass) - : AlphaStaticInst("(memacc)", machInst, __opClass) - { - } - - %(BasicExecDeclare)s - }; - }}; @@ -850,21 +816,6 @@ output decoder {{ } }}; -output exec {{ - Fault - EACompBase::execute(%(CPU_exec_context)s *, Trace::InstRecord *) - { - panic("attempt to execute eacomp"); - } - - Fault - MemAccBase::execute(%(CPU_exec_context)s *, Trace::InstRecord *) - { - panic("attempt to execute memacc"); - } -}}; - - def format LoadAddress(code) {{ iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code)) header_output = BasicDeclare.subst(iop) @@ -885,21 +836,25 @@ def template LoadStoreDeclare {{ /** * "Fake" effective address computation class for "%(mnemonic)s". */ - class EAComp : public EACompBase + class EAComp : public %(base_class)s { public: /// Constructor EAComp(MachInst machInst); + + %(BasicExecDeclare)s }; /** * "Fake" memory access instruction class for "%(mnemonic)s". */ - class MemAcc : public MemAccBase + class MemAcc : public %(base_class)s { public: /// Constructor MemAcc(MachInst machInst); + + %(BasicExecDeclare)s }; public: @@ -912,14 +867,17 @@ def template LoadStoreDeclare {{ }}; def template LoadStoreConstructor {{ + /** TODO: change op_class to AddrGenOp or something (requires + * creating new member of OpClass enum in op_class.hh, updating + * config files, etc.). */ inline %(class_name)s::EAComp::EAComp(MachInst machInst) - : EACompBase(machInst) + : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp) { %(ea_constructor)s; } inline %(class_name)s::MemAcc::MemAcc(MachInst machInst) - : MemAccBase(machInst, %(op_class)s) + : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s) { %(memacc_constructor)s; } @@ -932,6 +890,64 @@ def template LoadStoreConstructor {{ } }}; + +def template EACompExecute {{ + Fault + %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) + { + Addr EA; + Fault fault = No_Fault; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_rd)s; + %(code)s; + + if (fault == No_Fault) { + %(op_wb)s; + xc->setEA(EA); + } + + return fault; + } +}}; + +def template MemAccExecute {{ + Fault + %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) + { + Addr EA; + Fault fault = No_Fault; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_nonmem_rd)s; + EA = xc->getEA(); + + if (fault == No_Fault) { + %(op_mem_rd)s; + %(code)s; + } + + if (fault == No_Fault) { + %(op_mem_wb)s; + } + + if (fault == No_Fault) { + %(postacc_code)s; + } + + if (fault == No_Fault) { + %(op_nonmem_wb)s; + } + + return fault; + } +}}; + + def template LoadStoreExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) @@ -1022,18 +1038,33 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '', # Would be nice to autogenerate this list, but oh well. valid_mem_flags = ['LOCKED', 'NO_FAULT', 'EVICT_NEXT', 'PF_EXCLUSIVE'] - inst_flags = [] - mem_flags = [] - for f in flags: - if f in valid_mem_flags: - mem_flags.append(f) - else: - inst_flags.append(f) + mem_flags = [f for f in flags if f in valid_mem_flags] + inst_flags = [f for f in flags if f not in valid_mem_flags] + + # add hook to get effective addresses into execution trace output. + ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n' + # generate code block objects ea_cblk = CodeBlock(ea_code) memacc_cblk = CodeBlock(memacc_code) postacc_cblk = CodeBlock(postacc_code) + # Some CPU models execute the memory operation as an atomic unit, + # while others want to separate them into an effective address + # computation and a memory access operation. As a result, we need + # to generate three StaticInst objects. Note that the latter two + # are nested inside the larger "atomic" one. + + # generate InstObjParams for EAComp object + ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags) + + # generate InstObjParams for MemAcc object + memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags) + # in the split execution model, the MemAcc portion is responsible + # for the post-access code. + memacc_iop.postacc_code = postacc_cblk.code + + # generate InstObjParams for unified execution cblk = CodeBlock(ea_code + memacc_code + postacc_code) iop = InstObjParams(name, Name, base_class, cblk, inst_flags) @@ -1043,13 +1074,17 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '', iop.memacc_code = memacc_cblk.code iop.postacc_code = postacc_cblk.code - mem_flags = string.join(mem_flags, '|') - if mem_flags != '': - iop.constructor += '\n\tmemAccessFlags = ' + mem_flags + ';' + if mem_flags: + s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' + iop.constructor += s + memacc_iop.constructor += s # (header_output, decoder_output, decode_block, exec_output) return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop), - decode_template.subst(iop), exec_template.subst(iop)) + decode_template.subst(iop), + EACompExecute.subst(ea_iop) + + MemAccExecute.subst(memacc_iop) + + exec_template.subst(iop)) }}; @@ -1460,8 +1495,8 @@ output header {{ /// Constructor HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass, - StaticInstPtr _eaCompPtr, - StaticInstPtr _memAccPtr); + StaticInstPtr _eaCompPtr = nullStaticInstPtr, + StaticInstPtr _memAccPtr = nullStaticInstPtr); std::string generateDisassembly(Addr pc, const SymbolTable *symtab); }; diff --git a/arch/isa_parser.py b/arch/isa_parser.py index c0b5131de..18e4b0a45 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -1210,10 +1210,12 @@ class MemOperandTraits(OperandTraits): def makeWrite(self, op_desc): (size, type, is_signed) = operandSizeMap[op_desc.eff_ext] eff_type = 'uint%d_t' % size - return 'fault = xc->write((%s&)%s, EA, %s_flags,' \ - ' &%s_write_result);\n' \ + wb = 'fault = xc->write((%s&)%s, EA, %s_flags, &%s_write_result);\n' \ % (eff_type, op_desc.munged_name, op_desc.base_name, op_desc.base_name) + wb += 'if (traceData) { traceData->setData(%s); }' % \ + op_desc.munged_name + return wb class NPCOperandTraits(OperandTraits): def makeConstructor(self, op_desc): -- cgit v1.2.3