From 27960f6d858e92572d37604e92747d0b45591665 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 29 Feb 2004 14:54:52 -0500 Subject: fix rpcc arch/alpha/ev5.cc: actually implement the cycle count register arch/alpha/isa_desc: the rpcc instruction really just reads the cycle count register --HG-- extra : convert_revision : a0edec85672377a62b90950efc17b62b375220b1 --- arch/alpha/ev5.cc | 5 +++++ arch/alpha/isa_desc | 3 +-- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 96c51a2aa..551cbdabf 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -237,6 +237,11 @@ ExecContext::readIpr(int idx, Fault &fault) retval = ipr[idx]; break; + case AlphaISA::IPR_CC: + retval |= ipr[idx] & ULL(0xffffffff00000000); + retval |= curTick & ULL(0x00000000ffffffff); + break; + case AlphaISA::IPR_VA: // SFX: unlocks interrupt status registers retval = ipr[idx]; diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index c4d367211..0cfe5b452 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -2390,8 +2390,7 @@ decode OPCODE default Unknown::unknown() { format BasicOperate { 0xc000: rpcc({{ #ifdef FULL_SYSTEM - uint64_t cc = xc->readIpr(AlphaISA::IPR_CC, fault); - Ra = (cc<63:32> | curTick<31:0>); + Ra = xc->readIpr(AlphaISA::IPR_CC, fault); #else Ra = curTick; #endif -- cgit v1.2.3