From 12747d3084339d9db52d32e75215242b38474887 Mon Sep 17 00:00:00 2001 From: Andrew Schultz Date: Wed, 18 Feb 2004 21:38:55 -0500 Subject: Change the physical memory logic, and also add misspeculation fix to tlb index calls that are called from ExecContext::readIpr arch/alpha/ev5.cc: Fix misspeculation bugs for misspeculated IPR accesses --HG-- extra : convert_revision : c9ffcf9ef8123dfcaee1606c05aee8ad60d893d7 --- arch/alpha/alpha_memory.cc | 181 ++++++++++++++++++++++++--------------------- arch/alpha/alpha_memory.hh | 2 +- arch/alpha/ev5.cc | 6 +- 3 files changed, 100 insertions(+), 89 deletions(-) (limited to 'arch') diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index 7bdbea6c1..2f0dcfecf 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -282,19 +282,6 @@ AlphaItb::translate(MemReqPtr &req) const if (req->flags & PHYSICAL) { req->paddr = req->vaddr; - } else if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && - VA_SPACE(req->vaddr) == 2) { - // Check for "superpage" mapping: when SP<1> is set, and - // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>. - - // only valid in kernel mode - if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) { - fault(req->vaddr, req->xc); - acv++; - return Itb_Acv_Fault; - } - - req->paddr = req->vaddr & PA_IMPL_MASK; } else { // verify that this is a good virtual address if (!validVirtualAddress(req->vaddr)) { @@ -303,24 +290,41 @@ AlphaItb::translate(MemReqPtr &req) const return Itb_Acv_Fault; } - // not a physical address: need to look up pte - AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr), - DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); + // Check for "superpage" mapping: when SP<1> is set, and + // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>. + if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && + VA_SPACE(req->vaddr) == 2) { - if (!pte) { - fault(req->vaddr, req->xc); - misses++; - return Itb_Fault_Fault; - } + // only valid in kernel mode + if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) { + fault(req->vaddr, req->xc); + acv++; + return Itb_Acv_Fault; + } - req->paddr = PA_PFN2PA(pte->ppn) + VA_POFS(req->vaddr & ~3); + req->paddr = req->vaddr & PA_IMPL_MASK; + } else { + // not a physical address: need to look up pte + AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr), + DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); + + if (!pte) { + fault(req->vaddr, req->xc); + misses++; + return Itb_Fault_Fault; + } - // check permissions for this access - if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) { - // instruction access fault - fault(req->vaddr, req->xc); - acv++; - return Itb_Acv_Fault; + req->paddr = PA_PFN2PA(pte->ppn) + VA_POFS(req->vaddr & ~3); + + // check permissions for this access + if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) { + // instruction access fault + fault(req->vaddr, req->xc); + acv++; + return Itb_Acv_Fault; + } + + hits++; } } @@ -330,7 +334,6 @@ AlphaItb::translate(MemReqPtr &req) const checkCacheability(req); - hits++; return No_Fault; } @@ -453,27 +456,7 @@ AlphaDtb::translate(MemReqPtr &req, bool write) const if (req->flags & PHYSICAL) { req->paddr = req->vaddr; - } else if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && - VA_SPACE(req->vaddr) == 2) { - // Check for "superpage" mapping: when SP<1> is set, and - // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>. - - // only valid in kernel mode - if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) != AlphaISA::mode_kernel) { - fault(req->vaddr, - ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_ACV_MASK), - req->xc); - if (write) { write_acv++; } else { read_acv++; } - return Dtb_Acv_Fault; - } - - req->paddr = req->vaddr & PA_IMPL_MASK; } else { - if (write) - write_accesses++; - else - read_accesses++; - // verify that this is a good virtual address if (!validVirtualAddress(req->vaddr)) { fault(req->vaddr, @@ -485,48 +468,72 @@ AlphaDtb::translate(MemReqPtr &req, bool write) const return Dtb_Fault_Fault; } - // not a physical address: need to look up pte - AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr), - DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); - - if (!pte) { - // page fault - fault(req->vaddr, - ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_DTB_MISS_MASK), - req->xc); - if (write) { write_misses++; } else { read_misses++; } - return (req->flags & VPTE) ? Pdtb_Miss_Fault : Ndtb_Miss_Fault; - } - - req->paddr = PA_PFN2PA(pte->ppn) | VA_POFS(req->vaddr); + // Check for "superpage" mapping: when SP<1> is set, and + // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>. + if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && + VA_SPACE(req->vaddr) == 2) { - if (write) { - if (!(pte->xwe & MODE2MASK(mode))) { - // declare the instruction access fault - fault(req->vaddr, MM_STAT_WR_MASK | MM_STAT_ACV_MASK | - (pte->fonw ? MM_STAT_FONW_MASK : 0), - req->xc); - write_acv++; - return Dtb_Fault_Fault; - } - if (pte->fonw) { - fault(req->vaddr, MM_STAT_WR_MASK | MM_STAT_FONW_MASK, + // only valid in kernel mode + if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) != + AlphaISA::mode_kernel) { + fault(req->vaddr, + ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_ACV_MASK), req->xc); - write_acv++; - return Dtb_Fault_Fault; + if (write) { write_acv++; } else { read_acv++; } + return Dtb_Acv_Fault; } + + req->paddr = req->vaddr & PA_IMPL_MASK; } else { - if (!(pte->xre & MODE2MASK(mode))) { + if (write) + write_accesses++; + else + read_accesses++; + + // not a physical address: need to look up pte + AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr), + DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); + + if (!pte) { + // page fault fault(req->vaddr, - MM_STAT_ACV_MASK | (pte->fonr ? MM_STAT_FONR_MASK : 0), + ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_DTB_MISS_MASK), req->xc); - read_acv++; - return Dtb_Acv_Fault; + if (write) { write_misses++; } else { read_misses++; } + return (req->flags & VPTE) ? Pdtb_Miss_Fault : Ndtb_Miss_Fault; } - if (pte->fonr) { - fault(req->vaddr, MM_STAT_FONR_MASK, req->xc); - read_acv++; - return Dtb_Fault_Fault; + + req->paddr = PA_PFN2PA(pte->ppn) | VA_POFS(req->vaddr); + + if (write) { + if (!(pte->xwe & MODE2MASK(mode))) { + // declare the instruction access fault + fault(req->vaddr, MM_STAT_WR_MASK | MM_STAT_ACV_MASK | + (pte->fonw ? MM_STAT_FONW_MASK : 0), + req->xc); + write_acv++; + return Dtb_Fault_Fault; + } + if (pte->fonw) { + fault(req->vaddr, MM_STAT_WR_MASK | MM_STAT_FONW_MASK, + req->xc); + write_acv++; + return Dtb_Fault_Fault; + } + } else { + if (!(pte->xre & MODE2MASK(mode))) { + fault(req->vaddr, + MM_STAT_ACV_MASK | + (pte->fonr ? MM_STAT_FONR_MASK : 0), + req->xc); + read_acv++; + return Dtb_Acv_Fault; + } + if (pte->fonr) { + fault(req->vaddr, MM_STAT_FONR_MASK, req->xc); + read_acv++; + return Dtb_Fault_Fault; + } } } @@ -546,10 +553,12 @@ AlphaDtb::translate(MemReqPtr &req, bool write) const } AlphaISA::PTE & -AlphaTlb::index() +AlphaTlb::index(bool advance) { AlphaISA::PTE *pte = &table[nlu]; - nextnlu(); + + if (advance) + nextnlu(); return *pte; } diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh index 482a13eee..999eec228 100644 --- a/arch/alpha/alpha_memory.hh +++ b/arch/alpha/alpha_memory.hh @@ -56,7 +56,7 @@ class AlphaTlb : public SimObject int getsize() const { return size; } - AlphaISA::PTE &index(); + AlphaISA::PTE &index(bool advance = true); void insert(Addr vaddr, AlphaISA::PTE &pte); void flushAll(); diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 8494ee9f6..aaa81a58d 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -240,7 +240,9 @@ ExecContext::readIpr(int idx, Fault &fault) case AlphaISA::IPR_VA: // SFX: unlocks interrupt status registers retval = ipr[idx]; - regs.intrlock = false; + + if (!misspeculating()) + regs.intrlock = false; break; case AlphaISA::IPR_VA_FORM: @@ -253,7 +255,7 @@ ExecContext::readIpr(int idx, Fault &fault) case AlphaISA::IPR_DTB_PTE: { - AlphaISA::PTE &pte = dtb->index(); + AlphaISA::PTE &pte = dtb->index(!misspeculating()); retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; -- cgit v1.2.3 From 6f5e104fc5683ace0c17ddb402bf8d40330f60aa Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 26 Feb 2004 07:05:36 -0800 Subject: Make SW prefetch flag a parameter again, and add code to make it actually do something on FullCPU. Still disabled, as it causes detailed-boot to hang when you turn it on. arch/alpha/isa_desc: Add EAComp and MemAcc pseudo-instructions to prefetch StaticInst. cpu/simple_cpu/simple_cpu.hh: Changed prefetch() return type from Fault to void. --HG-- extra : convert_revision : c7cb42682bfea6af117c87d4dfdb06176b6fe6b7 --- arch/alpha/isa_desc | 42 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 75b2f4138..6a95b4e04 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1000,10 +1000,50 @@ def template PrefetchDeclare {{ */ class %(class_name)s : public %(base_class)s { + protected: + + /** + * "Fake" effective address computation class for "%(mnemonic)s". + */ + class EAComp : public EACompBase + { + public: + /// Constructor + EAComp(MachInst machInst) + : EACompBase(machInst) + { + %(ea_constructor)s; + } + }; + + /** + * "Fake" memory access instruction class for "%(mnemonic)s". + */ + class MemAcc : public MemAccBase + { + public: + /// Constructor + MemAcc(MachInst machInst) + : MemAccBase(machInst, %(op_class)s) + { + %(memacc_constructor)s; + } + }; + + /// Pointer to EAComp object. + StaticInstPtr eaCompPtr; + /// Pointer to MemAcc object. + StaticInstPtr memAccPtr; + public: + + StaticInstPtr eaCompInst() { return eaCompPtr; } + StaticInstPtr memAccInst() { return memAccPtr; } + /// Constructor %(class_name)s(MachInst machInst) - : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s), + eaCompPtr(new EAComp(machInst)), memAccPtr(new MemAcc(machInst)) { %(constructor)s; } -- cgit v1.2.3 From c3784e37ceba78eee92f46ed92aa2462e238a206 Mon Sep 17 00:00:00 2001 From: Erik Hallnor Date: Fri, 27 Feb 2004 00:45:21 -0500 Subject: Initial copy support in the pipeline. Add copypal counting. arch/alpha/osfpal.cc: Add a string for copypal. arch/alpha/osfpal.hh: Add a code for copypal. cpu/static_inst.hh: Add an IsCopy flag. --HG-- extra : convert_revision : 19e3d90368454806029ad492eace19cd0924fe9f --- arch/alpha/osfpal.cc | 2 +- arch/alpha/osfpal.hh | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/alpha/osfpal.cc b/arch/alpha/osfpal.cc index 4c0ace8c0..90d645ef1 100644 --- a/arch/alpha/osfpal.cc +++ b/arch/alpha/osfpal.cc @@ -224,8 +224,8 @@ namespace { 0, // 0xbc 0, // 0xbd "nphalt", // 0xbe + "copypal", // 0xbf #if 0 - 0, // 0xbf 0, // 0xc0 0, // 0xc1 0, // 0xc2 diff --git a/arch/alpha/osfpal.hh b/arch/alpha/osfpal.hh index 61e545306..419235b4a 100644 --- a/arch/alpha/osfpal.hh +++ b/arch/alpha/osfpal.hh @@ -70,6 +70,7 @@ struct PAL gentrap = 0xaa, clrfen = 0xae, nphalt = 0xbe, + copypal = 0xbf, NumCodes }; -- cgit v1.2.3 From cfb6f8fd01e19dbd0b3ce5cfa28d6f78f617e954 Mon Sep 17 00:00:00 2001 From: Erik Hallnor Date: Fri, 27 Feb 2004 02:40:43 -0500 Subject: Added copy instructions to the ISA. Well it didn't break anything yet... arch/alpha/isa_desc: Add copy_load and copy_store insts (ldf and stf respectively) cpu/simple_cpu/simple_cpu.hh: Add copy functions to SimpleCPU as well --HG-- extra : convert_revision : 1fa041da582b418c47d4eefc22dabba978a50e2d --- arch/alpha/isa_desc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 6a95b4e04..46fb306a4 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1854,6 +1854,9 @@ decode OPCODE default Unknown::unknown() { 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }}); 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED); 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED); + 0x20: copy_load({{EA = Ra;}}, + {{memAccessObj->copySrcTranslate(EA);}}, + IsMemRef, IsLoad, IsCopy); } format LoadOrPrefetch { @@ -1873,6 +1876,9 @@ decode OPCODE default Unknown::unknown() { 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }}); 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }}); 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }}); + 0x24: copy_store({{EA = Rb;}}, + {{memAccessObj->copy(EA);}}, + IsMemRef, IsStore, IsCopy); } format StoreCond { -- cgit v1.2.3 From c79deda8cd404565bbd277e67b3533b6c13fac74 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 28 Feb 2004 17:21:32 -0500 Subject: Fix handling of rpcc in full-system mode. arch/alpha/ev5.cc: Handle writing IPR_CC and IPR_CC_CTL slightly more intelligently. (Very slightly). arch/alpha/isa_desc: Upper half of rpcc result comes from value written to IPR_CC, not actual cycle counter. --HG-- extra : convert_revision : 7161989db8a3f040d0558e2e5a1a162ed1cb4125 --- arch/alpha/ev5.cc | 16 ++++++++++++++-- arch/alpha/isa_desc | 9 ++++++++- 2 files changed, 22 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index aaa81a58d..96c51a2aa 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -329,13 +329,25 @@ ExecContext::setIpr(int idx, uint64_t val) case AlphaISA::IPR_PAL_BASE: case AlphaISA::IPR_IC_PERR_STAT: case AlphaISA::IPR_DC_PERR_STAT: - case AlphaISA::IPR_CC_CTL: - case AlphaISA::IPR_CC: case AlphaISA::IPR_PMCTR: // write entire quad w/ no side-effect ipr[idx] = val; break; + case AlphaISA::IPR_CC_CTL: + // This IPR resets the cycle counter. We assume this only + // happens once... let's verify that. + assert(ipr[idx] == 0); + ipr[idx] = 1; + break; + + case AlphaISA::IPR_CC: + // This IPR only writes the upper 64 bits. It's ok to write + // all 64 here since we mask out the lower 32 in rpcc (see + // isa_desc). + ipr[idx] = val; + break; + case AlphaISA::IPR_PALtemp23: // write entire quad w/ no side-effect ipr[idx] = val; diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 46fb306a4..c4d367211 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -2388,7 +2388,14 @@ decode OPCODE default Unknown::unknown() { } format BasicOperate { - 0xc000: rpcc({{ Ra = curTick; }}); + 0xc000: rpcc({{ +#ifdef FULL_SYSTEM + uint64_t cc = xc->readIpr(AlphaISA::IPR_CC, fault); + Ra = (cc<63:32> | curTick<31:0>); +#else + Ra = curTick; +#endif + }}); // All of the barrier instructions below do nothing in // their execute() methods (hence the empty code blocks). -- cgit v1.2.3 From 27960f6d858e92572d37604e92747d0b45591665 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 29 Feb 2004 14:54:52 -0500 Subject: fix rpcc arch/alpha/ev5.cc: actually implement the cycle count register arch/alpha/isa_desc: the rpcc instruction really just reads the cycle count register --HG-- extra : convert_revision : a0edec85672377a62b90950efc17b62b375220b1 --- arch/alpha/ev5.cc | 5 +++++ arch/alpha/isa_desc | 3 +-- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 96c51a2aa..551cbdabf 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -237,6 +237,11 @@ ExecContext::readIpr(int idx, Fault &fault) retval = ipr[idx]; break; + case AlphaISA::IPR_CC: + retval |= ipr[idx] & ULL(0xffffffff00000000); + retval |= curTick & ULL(0x00000000ffffffff); + break; + case AlphaISA::IPR_VA: // SFX: unlocks interrupt status registers retval = ipr[idx]; diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index c4d367211..0cfe5b452 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -2390,8 +2390,7 @@ decode OPCODE default Unknown::unknown() { format BasicOperate { 0xc000: rpcc({{ #ifdef FULL_SYSTEM - uint64_t cc = xc->readIpr(AlphaISA::IPR_CC, fault); - Ra = (cc<63:32> | curTick<31:0>); + Ra = xc->readIpr(AlphaISA::IPR_CC, fault); #else Ra = curTick; #endif -- cgit v1.2.3 From cbc42f1d71323fa94ad2b5262258c1d6b1c0b0bf Mon Sep 17 00:00:00 2001 From: Erik Hallnor Date: Sun, 29 Feb 2004 22:41:11 -0500 Subject: Remove copys from isa_desc, and implement a store and forward bus bridge arch/alpha/isa_desc: Just to make sure, remove the new copy instructions until everything works. --HG-- extra : convert_revision : cdd3d4c8fa415175aaee04f4a99340dcf82dbc3a --- arch/alpha/isa_desc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 0cfe5b452..a7665210f 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1854,9 +1854,9 @@ decode OPCODE default Unknown::unknown() { 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }}); 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED); 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED); - 0x20: copy_load({{EA = Ra;}}, - {{memAccessObj->copySrcTranslate(EA);}}, - IsMemRef, IsLoad, IsCopy); + //0x20: copy_load({{EA = Ra;}}, + // {{memAccessObj->copySrcTranslate(EA);}}, + // IsMemRef, IsLoad, IsCopy); } format LoadOrPrefetch { @@ -1876,9 +1876,9 @@ decode OPCODE default Unknown::unknown() { 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }}); 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }}); 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }}); - 0x24: copy_store({{EA = Rb;}}, - {{memAccessObj->copy(EA);}}, - IsMemRef, IsStore, IsCopy); + //0x24: copy_store({{EA = Rb;}}, + // {{memAccessObj->copy(EA);}}, + // IsMemRef, IsStore, IsCopy); } format StoreCond { -- cgit v1.2.3 From 7c089b2001afb93fe51b1a89456b15fd0d00c794 Mon Sep 17 00:00:00 2001 From: Erik Hallnor Date: Thu, 4 Mar 2004 14:57:57 -0500 Subject: Copy implementations arch/alpha/isa_desc: Need to return fault for copy operations. cpu/exec_context.hh: Add temporary storage to pass source address from copy load to copy store cpu/simple_cpu/simple_cpu.cc: Implement copy functions. cpu/simple_cpu/simple_cpu.hh: Return fault --HG-- extra : convert_revision : 98e5ce563449d6057ba45c70eece9235f1649a90 --- arch/alpha/isa_desc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 46fb306a4..41f7388e0 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1855,7 +1855,7 @@ decode OPCODE default Unknown::unknown() { 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED); 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED); 0x20: copy_load({{EA = Ra;}}, - {{memAccessObj->copySrcTranslate(EA);}}, + {{fault = memAccessObj->copySrcTranslate(EA);}}, IsMemRef, IsLoad, IsCopy); } @@ -1877,7 +1877,7 @@ decode OPCODE default Unknown::unknown() { 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }}); 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }}); 0x24: copy_store({{EA = Rb;}}, - {{memAccessObj->copy(EA);}}, + {{fault =memAccessObj->copy(EA);}}, IsMemRef, IsStore, IsCopy); } -- cgit v1.2.3 From 1d09cd71a411a6f4e81fe60a2b180d8b5aa5de86 Mon Sep 17 00:00:00 2001 From: Erik Hallnor Date: Thu, 4 Mar 2004 20:03:38 -0500 Subject: Reenable functioning copies. arch/alpha/isa_desc: Reenable copies. --HG-- extra : convert_revision : 99259c0ff65e742e617cba1c14f5d1bf4be2fee8 --- arch/alpha/isa_desc | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 56e7cb31c..0da087f97 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1854,10 +1854,9 @@ decode OPCODE default Unknown::unknown() { 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }}); 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED); 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED); - {{fault = memAccessObj->copySrcTranslate(EA);}}, - //0x20: copy_load({{EA = Ra;}}, - // {{memAccessObj->copySrcTranslate(EA);}}, - // IsMemRef, IsLoad, IsCopy); + 0x20: copy_load({{EA = Ra;}}, + {{ fault = memAccessObj->copySrcTranslate(EA);}}, + IsMemRef, IsLoad, IsCopy); } format LoadOrPrefetch { @@ -1877,10 +1876,9 @@ decode OPCODE default Unknown::unknown() { 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }}); 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }}); 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }}); - {{fault =memAccessObj->copy(EA);}}, - //0x24: copy_store({{EA = Rb;}}, - // {{memAccessObj->copy(EA);}}, - // IsMemRef, IsStore, IsCopy); + 0x24: copy_store({{EA = Rb;}}, + {{ fault = memAccessObj->copy(EA);}}, + IsMemRef, IsStore, IsCopy); } format StoreCond { -- cgit v1.2.3