From 4328480b5602decbcc7239e1884324ce23eaa3ec Mon Sep 17 00:00:00 2001
From: Nathan Binkert <binkertn@umich.edu>
Date: Wed, 10 Nov 2004 18:37:19 -0500
Subject: Don't use the global check_interrupts variable.  Add a per-cpu
 checkInterrupts variable and use that to determine whether an interrupt can
 occur on a given cycle.

arch/alpha/ev5.cc:
    XC -> CPU (and xc -> CPU) since we're really talking about a CPU here
    Don't use the global check_interrupts variable.  Add a per-cpu
    checkInterrupts variable and use that to determine whether an interrupt
    can occur on a given cycle.

--HG--
extra : convert_revision : be4c0247e5834005c60a45796a222cffd327b64e
---
 arch/alpha/ev5.cc | 24 +++++++++++-------------
 1 file changed, 11 insertions(+), 13 deletions(-)

(limited to 'arch')

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 8b95e8b3d..aa52916b9 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -101,17 +101,17 @@ AlphaISA::initIPRs(RegFile *regs)
 }
 
 
-template <class XC>
+template <class CPU>
 void
-AlphaISA::processInterrupts(XC *xc)
+AlphaISA::processInterrupts(CPU *cpu)
 {
     //Check if there are any outstanding interrupts
     //Handle the interrupts
     int ipl = 0;
     int summary = 0;
-    IntReg *ipr = xc->getIprPtr();
+    IntReg *ipr = cpu->getIprPtr();
 
-    check_interrupts = 0;
+    cpu->checkInterrupts = false;
 
     if (ipr[IPR_ASTRR])
         panic("asynchronous traps not implemented\n");
@@ -127,7 +127,7 @@ AlphaISA::processInterrupts(XC *xc)
         }
     }
 
-    uint64_t interrupts = xc->intr_status();
+    uint64_t interrupts = cpu->intr_status();
 
     if (interrupts) {
         for (int i = INTLEVEL_EXTERNAL_MIN;
@@ -143,22 +143,22 @@ AlphaISA::processInterrupts(XC *xc)
     if (ipl && ipl > ipr[IPR_IPLR]) {
         ipr[IPR_ISR] = summary;
         ipr[IPR_INTID] = ipl;
-        xc->trap(Interrupt_Fault);
+        cpu->trap(Interrupt_Fault);
         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
                 ipr[IPR_IPLR], ipl, summary);
     }
 
 }
 
-template <class XC>
+template <class CPU>
 void
-AlphaISA::zeroRegisters(XC *xc)
+AlphaISA::zeroRegisters(CPU *cpu)
 {
     // Insure ISA semantics
     // (no longer very clean due to the change in setIntReg() in the
     // cpu model.  Consider changing later.)
-    xc->xc->setIntReg(ZeroReg, 0);
-    xc->xc->setFloatRegDouble(ZeroReg, 0.0);
+    cpu->xc->setIntReg(ZeroReg, 0);
+    cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
 }
 
 void
@@ -220,8 +220,6 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
     // that's it! (orders of magnitude less painful than x86)
 }
 
-bool AlphaISA::check_interrupts = false;
-
 Fault
 ExecContext::hwrei()
 {
@@ -238,7 +236,7 @@ ExecContext::hwrei()
         if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
             AlphaISA::swap_palshadow(&regs, false);
 
-        AlphaISA::check_interrupts = true;
+        cpu->checkInterrupts = true;
     }
 
     // FIXME: XXX check for interrupts? XXX
-- 
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