From 48f2626eaca40d4cf0b692f2ac8ec07eb5586516 Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Fri, 14 Apr 2006 03:42:02 -0400
Subject: These fixes now allow all of the 20 mips tests to work properly!
 Floating Point Mips Tests still need to be added, tested, and debugged.

arch/mips/isa/decoder.isa:
    Fix mult and multu instructions. This semantic error causes the problem: <int64> = <int32> * <int32>. Although I was placing
    the output into a 64-bit integer the multiply was just doing a 32-bit multiply so the solution is to just use
    the 'sd' & 'ud' operands so that the ISA parser will use the int64_t and uint64_t types in calculation.
arch/mips/isa/formats/int.isa:
    Trace output fix. Don't print first comma unless there is a destination register for sure!

--HG--
extra : convert_revision : 2c503dca70b104fed0b58454975f745dd3cc2eee
---
 arch/mips/isa/decoder.isa     | 14 ++++++--------
 arch/mips/isa/formats/int.isa |  3 +--
 2 files changed, 7 insertions(+), 10 deletions(-)

(limited to 'arch')

diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index ffedfbca8..eaa7b7248 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -137,17 +137,15 @@ decode OPCODE_HI default Unknown::unknown() {
             0x3: decode FUNCTION_LO {
                 format IntOp {
                     0x0: mult({{
-                        int64_t temp1 = Rs.sw * Rt.sw;
+                        int64_t temp1 = Rs.sd * Rt.sd;
                         xc->setMiscReg(Hi,temp1<63:32>);
                         xc->setMiscReg(Lo,temp1<31:0>);
                     }});
 
                     0x1: multu({{
-                        uint64_t temp1 = Rs.uw * Rt.uw;
-                        uint32_t hi_val = temp1<63:32>;
-                        uint32_t lo_val = temp1<31:0>;
-                        xc->setMiscReg(Hi,hi_val);
-                        xc->setMiscReg(Lo,lo_val);
+                        uint64_t temp1 = Rs.ud * Rt.ud;
+                        xc->setMiscReg(Hi,temp1<63:32>);
+                        xc->setMiscReg(Lo,temp1<31:0>);
                     }});
 
                     0x2: div({{
@@ -156,8 +154,8 @@ decode OPCODE_HI default Unknown::unknown() {
                     }});
 
                     0x3: divu({{
-                      xc->setMiscReg(Hi,Rs.uw % Rt.uw);
-                      xc->setMiscReg(Lo,Rs.uw / Rt.uw);
+                        xc->setMiscReg(Hi,Rs.uw % Rt.uw);
+                        xc->setMiscReg(Lo,Rs.uw / Rt.uw);
                     }});
                 }
             }
diff --git a/arch/mips/isa/formats/int.isa b/arch/mips/isa/formats/int.isa
index 98e58f7f2..7d38b9ff5 100644
--- a/arch/mips/isa/formats/int.isa
+++ b/arch/mips/isa/formats/int.isa
@@ -64,10 +64,9 @@ output decoder {{
             // it's generally implicit
             if (_numDestRegs > 0) {
                 printReg(ss, _destRegIdx[0]);
+                ss << ",";
             }
 
-            ss << ",";
-
             // just print the first two source regs... if there's
             // a third one, it's a read-modify-write dest (Rc),
             // e.g. for CMOVxx
-- 
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