From 6964ecd1cf14f294a300e91bc5b65042d03952d4 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Fri, 28 May 2004 14:42:59 -0400
Subject: Updated FastCPU model with all the recent changes.

arch/alpha/ev5.cc:
    Updated to support new forms of setIntReg and setFloatRegDouble.  Will need to be cleaned up in the future.
arch/isa_parser.py:
    Added in FastCPU model.

--HG--
extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db
---
 arch/alpha/ev5.cc  | 6 ++++--
 arch/isa_parser.py | 3 +++
 2 files changed, 7 insertions(+), 2 deletions(-)

(limited to 'arch')

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index e88f6d0a3..ecf66f4f5 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -153,8 +153,10 @@ void
 AlphaISA::zeroRegisters(XC *xc)
 {
     // Insure ISA semantics
-    xc->setIntReg(ZeroReg, 0);
-    xc->setFloatRegDouble(ZeroReg, 0.0);
+    // (no longer very clean due to the change in setIntReg() in the
+    // cpu model.  Consider changing later.)
+    xc->xc->setIntReg(ZeroReg, 0);
+    xc->xc->setFloatRegDouble(ZeroReg, 0.0);
 }
 
 void
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 7f77241be..c808c2565 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -630,6 +630,9 @@ class CpuModel:
 CpuModel('SimpleCPU', 'simple_cpu_exec.cc',
          '#include "cpu/simple_cpu/simple_cpu.hh"',
          { 'CPU_exec_context': 'SimpleCPU' })
+CpuModel('FastCPU', 'fast_cpu_exec.cc',
+         '#include "cpu/fast_cpu/fast_cpu.hh"',
+         { 'CPU_exec_context': 'FastCPU' })
 CpuModel('FullCPU', 'full_cpu_exec.cc',
          '#include "cpu/full_cpu/dyn_inst.hh"',
          { 'CPU_exec_context': 'DynInst' })
-- 
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