From 4c55d26e664f870d56889097939569c4b07c6de2 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 18 May 2004 16:09:02 -0700 Subject: Replace explicit xc->misspeculating() tests in execute() methods with an IsNonSpeculative flag. No effect on results of non-full-system or SimpleCPU. Very small impact on full-system FullCPU runs since old wrong-path call_pal insts used to change the PC, where now they're treated as no-ops. arch/alpha/isa_desc: Get rid of xc->misspeculating() checks, use IsNonSpeculative flag instead. cpu/static_inst.hh: Add IsNonSpeculative flag and isNonSpeculative() method to test it. --HG-- extra : convert_revision : 7ec536bfc28b905c429c09eb920ed73ef2beeeba --- arch/alpha/isa_desc | 151 ++++++++++++++++++++-------------------------------- 1 file changed, 57 insertions(+), 94 deletions(-) (limited to 'arch') diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index f964101df..8641c2880 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1374,8 +1374,8 @@ output decoder {{ } }}; -def format EmulatedCallPal(code) {{ - iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code)) +def format EmulatedCallPal(code, *flags) {{ + iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code), flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) @@ -1436,8 +1436,8 @@ output decoder {{ } }}; -def format CallPal(code) {{ - iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code)) +def format CallPal(code, *flags) {{ + iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code), flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) @@ -1588,6 +1588,9 @@ output header {{ FailUnimplemented(const char *_mnemonic, MachInst _machInst) : AlphaStaticInst(_mnemonic, _machInst, No_OpClass) { + // don't call execute() (which panics) if we're on a + // speculative path + flags[IsNonSpeculative] = true; } %(BasicExecDeclare)s @@ -1615,6 +1618,9 @@ output header {{ WarnUnimplemented(const char *_mnemonic, MachInst _machInst) : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false) { + // don't call execute() (which panics) if we're on a + // speculative path + flags[IsNonSpeculative] = true; } %(BasicExecDeclare)s @@ -1646,9 +1652,8 @@ output exec {{ FailUnimplemented::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) { - if (!xc->misspeculating()) - panic("attempt to execute unimplemented instruction '%s' " - "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE); + panic("attempt to execute unimplemented instruction '%s' " + "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE); return Unimplemented_Opcode_Fault; } @@ -1656,42 +1661,24 @@ output exec {{ WarnUnimplemented::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) { - if (!xc->misspeculating()) - if (!warned) { - warn("instruction '%s' unimplemented\n", mnemonic); - warned = true; - } + if (!warned) { + warn("instruction '%s' unimplemented\n", mnemonic); + warned = true; + } return No_Fault; } }}; -def template WarnUnimplDeclare {{ - /** - * Static instruction class for "%(mnemonic)s". - */ - class %(class_name)s : public %(base_class)s - { - public: - /// Constructor - %(class_name)s(MachInst machInst) - : %(base_class)s("%(mnemonic)s", machInst) - { - } - }; -}}; - - def format FailUnimpl() {{ iop = InstObjParams(name, 'FailUnimplemented') decode_block = BasicDecodeWithMnemonic.subst(iop) }}; def format WarnUnimpl() {{ - iop = InstObjParams(name, Name, 'WarnUnimplemented') - header_output = WarnUnimplDeclare.subst(iop) - decode_block = BasicDecode.subst(iop) + iop = InstObjParams(name, 'WarnUnimplemented') + decode_block = BasicDecodeWithMnemonic.subst(iop) }}; output header {{ @@ -1707,6 +1694,9 @@ output header {{ Unknown(MachInst _machInst) : AlphaStaticInst("unknown", _machInst, No_OpClass) { + // don't call execute() (which panics) if we're on a + // speculative path + flags[IsNonSpeculative] = true; } %(BasicExecDeclare)s @@ -1733,9 +1723,8 @@ output exec {{ Fault Unknown::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) { - if (!xc->misspeculating()) - panic("attempt to execute unknown instruction " - "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE); + panic("attempt to execute unknown instruction " + "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE); return Unimplemented_Opcode_Fault; } }}; @@ -2420,16 +2409,12 @@ decode OPCODE default Unknown::unknown() { format BasicOperate { 0xe000: rc({{ Ra = xc->readIntrFlag(); - if (!xc->misspeculating()) { - xc->setIntrFlag(0); - } - }}); + xc->setIntrFlag(0); + }}, IsNonSpeculative); 0xf000: rs({{ Ra = xc->readIntrFlag(); - if (!xc->misspeculating()) { - xc->setIntrFlag(1); - } - }}); + xc->setIntrFlag(1); + }}, IsNonSpeculative); } #else format FailUnimpl { @@ -2449,38 +2434,26 @@ decode OPCODE default Unknown::unknown() { fault = Unimplemented_Opcode_Fault; } else { - bool dopal = true; - - if (!xc->misspeculating()) { - // check to see if simulator wants to do something special - // on this PAL call (including maybe suppress it) - dopal = xc->simPalCheck(palFunc); - - if (dopal) { - AlphaISA::swap_palshadow(&xc->xcBase()->regs, true); - xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC); - } - } + // check to see if simulator wants to do something special + // on this PAL call (including maybe suppress it) + bool dopal = xc->simPalCheck(palFunc); - // if we're misspeculating, it's still safe (if - // unrealistic) to set NPC, as the control-flow change - // won't get committed. if (dopal) { + AlphaISA::swap_palshadow(&xc->xcBase()->regs, true); + xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC); NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset; } } - }}); + }}, IsNonSpeculative); #else 0x00: decode PALFUNC { format EmulatedCallPal { 0x00: halt ({{ - if (!xc->misspeculating()) - SimExit(curTick, "halt instruction encountered"); - }}); + SimExit(curTick, "halt instruction encountered"); + }}, IsNonSpeculative); 0x83: callsys({{ - if (!xc->misspeculating()) - xc->syscall(); - }}); + xc->syscall(); + }}, IsNonSpeculative); // Read uniq reg into ABI return value register (r0) 0x9e: rduniq({{ R0 = Runiq; }}); // Write uniq reg with value from ABI arg register (r16) @@ -2514,46 +2487,36 @@ decode OPCODE default Unknown::unknown() { // M5 special opcodes use the reserved 0x01 opcode space 0x01: decode M5FUNC { 0x00: arm({{ - if (!xc->misspeculating()) - AlphaPseudo::arm(xc->xcBase()); - }}); + AlphaPseudo::arm(xc->xcBase()); + }}, IsNonSpeculative); 0x01: quiesce({{ - if (!xc->misspeculating()) - AlphaPseudo::quiesce(xc->xcBase()); - }}); + AlphaPseudo::quiesce(xc->xcBase()); + }}, IsNonSpeculative); 0x10: ivlb({{ - if (!xc->misspeculating()) - AlphaPseudo::ivlb(xc->xcBase()); - }}, No_OpClass); + AlphaPseudo::ivlb(xc->xcBase()); + }}, No_OpClass, IsNonSpeculative); 0x11: ivle({{ - if (!xc->misspeculating()) - AlphaPseudo::ivle(xc->xcBase()); - }}, No_OpClass); + AlphaPseudo::ivle(xc->xcBase()); + }}, No_OpClass, IsNonSpeculative); 0x20: m5exit_old({{ - if (!xc->misspeculating()) - AlphaPseudo::m5exit_old(xc->xcBase()); - }}, No_OpClass); + AlphaPseudo::m5exit_old(xc->xcBase()); + }}, No_OpClass, IsNonSpeculative); 0x21: m5exit({{ - if (!xc->misspeculating()) - AlphaPseudo::m5exit(xc->xcBase()); - }}, No_OpClass); + AlphaPseudo::m5exit(xc->xcBase()); + }}, No_OpClass, IsNonSpeculative); 0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }}); 0x40: resetstats({{ - if (!xc->misspeculating()) - AlphaPseudo::resetstats(xc->xcBase()); - }}); + AlphaPseudo::resetstats(xc->xcBase()); + }}, IsNonSpeculative); 0x41: dumpstats({{ - if (!xc->misspeculating()) - AlphaPseudo::dumpstats(xc->xcBase()); - }}); + AlphaPseudo::dumpstats(xc->xcBase()); + }}, IsNonSpeculative); 0x42: dumpresetstats({{ - if (!xc->misspeculating()) - AlphaPseudo::dumpresetstats(xc->xcBase()); - }}); + AlphaPseudo::dumpresetstats(xc->xcBase()); + }}, IsNonSpeculative); 0x43: m5checkpoint({{ - if (!xc->misspeculating()) - AlphaPseudo::m5checkpoint(xc->xcBase()); - }}); + AlphaPseudo::m5checkpoint(xc->xcBase()); + }}, IsNonSpeculative); } } -- cgit v1.2.3 From 27a6e8258dabef233bc1681649b871bf150878ed Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 18 May 2004 22:09:13 -0700 Subject: Add a level of indirection to the register accessors used in instruction execute methods. Register i now means the instruction's i'th src (or dest) operand, not architectural register i. Current models that use the architectural reg index can look that up easily in the instruction object. Future models that do register renaming should find this much simpler to deal with. arch/isa_parser.py: Generate register accessors with an extra level of indirection. cpu/simple_cpu/simple_cpu.hh: Modify register accessors to use an extra level of indirection. --HG-- extra : convert_revision : f4c7d6bfa92fb2ea6251f31ee368809c3643f08f --- arch/isa_parser.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/isa_parser.py b/arch/isa_parser.py index 621720709..7f77241be 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -1057,10 +1057,10 @@ class IntRegOperandTraits(OperandTraits): if (type == 'float' or type == 'double'): error(0, 'Attempt to read integer register as FP') if (size == self.dflt_size): - return '%s = xc->readIntReg(_srcRegIdx[%d]);\n' % \ + return '%s = xc->readIntReg(this, %d);\n' % \ (op_desc.munged_name, op_desc.src_reg_idx) else: - return '%s = bits(xc->readIntReg(_srcRegIdx[%d]), %d, 0);\n' % \ + return '%s = bits(xc->readIntReg(this, %d), %d, 0);\n' % \ (op_desc.munged_name, op_desc.src_reg_idx, size-1) def makeWrite(self, op_desc): @@ -1074,7 +1074,7 @@ class IntRegOperandTraits(OperandTraits): wb = ''' { %s final_val = %s; - xc->setIntReg(_destRegIdx[%d], final_val);\n + xc->setIntReg(this, %d, final_val);\n if (traceData) { traceData->setData(final_val); } }''' % (self.dflt_type, final_val, op_desc.dest_reg_idx) return wb @@ -1107,7 +1107,7 @@ class FloatRegOperandTraits(OperandTraits): func = 'readFloatRegInt' if (size != self.dflt_size): bit_select = 1 - base = 'xc->%s(_srcRegIdx[%d] - FP_Base_DepTag)' % \ + base = 'xc->%s(this, %d)' % \ (func, op_desc.src_reg_idx) if bit_select: return '%s = bits(%s, %d, 0);\n' % \ @@ -1130,7 +1130,7 @@ class FloatRegOperandTraits(OperandTraits): wb = ''' { %s final_val = %s; - xc->%s(_destRegIdx[%d] - FP_Base_DepTag, final_val);\n + xc->%s(this, %d, final_val);\n if (traceData) { traceData->setData(final_val); } }''' % (type, final_val, func, op_desc.dest_reg_idx) return wb -- cgit v1.2.3 From b4405682d9f0d7bd01ff461a7e457f8dbbfff1a0 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 21 May 2004 13:03:17 -0400 Subject: Change the namespace Statistics to Stats --HG-- extra : convert_revision : 3084b292bbe2e8a392af8e99a31763ca0b0a9467 --- arch/alpha/alpha_memory.hh | 32 ++++++++++++++++---------------- arch/alpha/pseudo_inst.cc | 8 ++++---- 2 files changed, 20 insertions(+), 20 deletions(-) (limited to 'arch') diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh index 12196c44b..b5fc18255 100644 --- a/arch/alpha/alpha_memory.hh +++ b/arch/alpha/alpha_memory.hh @@ -80,10 +80,10 @@ class AlphaTLB : public SimObject class AlphaITB : public AlphaTLB { protected: - mutable Statistics::Scalar<> hits; - mutable Statistics::Scalar<> misses; - mutable Statistics::Scalar<> acv; - mutable Statistics::Formula accesses; + mutable Stats::Scalar<> hits; + mutable Stats::Scalar<> misses; + mutable Stats::Scalar<> acv; + mutable Stats::Formula accesses; protected: void fault(Addr pc, ExecContext *xc) const; @@ -98,18 +98,18 @@ class AlphaITB : public AlphaTLB class AlphaDTB : public AlphaTLB { protected: - mutable Statistics::Scalar<> read_hits; - mutable Statistics::Scalar<> read_misses; - mutable Statistics::Scalar<> read_acv; - mutable Statistics::Scalar<> read_accesses; - mutable Statistics::Scalar<> write_hits; - mutable Statistics::Scalar<> write_misses; - mutable Statistics::Scalar<> write_acv; - mutable Statistics::Scalar<> write_accesses; - Statistics::Formula hits; - Statistics::Formula misses; - Statistics::Formula acv; - Statistics::Formula accesses; + mutable Stats::Scalar<> read_hits; + mutable Stats::Scalar<> read_misses; + mutable Stats::Scalar<> read_acv; + mutable Stats::Scalar<> read_accesses; + mutable Stats::Scalar<> write_hits; + mutable Stats::Scalar<> write_misses; + mutable Stats::Scalar<> write_acv; + mutable Stats::Scalar<> write_accesses; + Stats::Formula hits; + Stats::Formula misses; + Stats::Formula acv; + Stats::Formula accesses; protected: void fault(Addr pc, uint64_t flags, ExecContext *xc) const; diff --git a/arch/alpha/pseudo_inst.cc b/arch/alpha/pseudo_inst.cc index 0a5c5b006..12dacebd9 100644 --- a/arch/alpha/pseudo_inst.cc +++ b/arch/alpha/pseudo_inst.cc @@ -37,7 +37,7 @@ #include "sim/stats.hh" using namespace std; -using namespace Statistics; +using namespace Stats; namespace AlphaPseudo { @@ -98,7 +98,7 @@ namespace AlphaPseudo Tick when = curTick + NS2Ticks(delay); Tick repeat = NS2Ticks(period); - using namespace Statistics; + using namespace Stats; SetupEvent(Reset, when, repeat); } @@ -114,7 +114,7 @@ namespace AlphaPseudo Tick when = curTick + NS2Ticks(delay); Tick repeat = NS2Ticks(period); - using namespace Statistics; + using namespace Stats; SetupEvent(Dump, when, repeat); } @@ -130,7 +130,7 @@ namespace AlphaPseudo Tick when = curTick + NS2Ticks(delay); Tick repeat = NS2Ticks(period); - using namespace Statistics; + using namespace Stats; SetupEvent(Dump|Reset, when, repeat); } -- cgit v1.2.3 From f622d74f81f6d0c451bc8437d19a38057bc0d164 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 21 May 2004 13:58:39 -0400 Subject: add a few statistics events arch/alpha/ev5.cc: Add an event for faults cpu/simple_cpu/simple_cpu.cc: add events for uncached reads/writes --HG-- extra : convert_revision : 747bdf12761e2de6ebbf54fecc9e0b71915b3a02 --- arch/alpha/ev5.cc | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index f037a34ac..96d54c54c 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -1,15 +1,14 @@ /* $Id$ */ -#include "targetarch/alpha_memory.hh" -#ifdef DEBUG -#include "sim/debug.hh" -#endif +#include "arch/alpha/alpha_memory.hh" +#include "arch/alpha/isa_traits.hh" +#include "arch/alpha/osfpal.hh" +#include "base/kgdb.h" +#include "base/remote_gdb.hh" +#include "base/stats/events.hh" #include "cpu/exec_context.hh" +#include "sim/debug.hh" #include "sim/sim_events.hh" -#include "targetarch/isa_traits.hh" -#include "base/remote_gdb.hh" -#include "base/kgdb.h" // for ALPHA_KENTRY_IF -#include "targetarch/osfpal.hh" #ifdef FULL_SYSTEM @@ -102,6 +101,8 @@ AlphaISA::initIPRs(RegFile *regs) void ExecContext::ev5_trap(Fault fault) { + Stats::recordEvent(csprintf("Fault %s", FaultName(fault))); + assert(!misspeculating()); kernelStats.fault(fault); -- cgit v1.2.3 From a896960cbfce76a0e0c8cfb5cbdfc805ce72577b Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 27 May 2004 17:46:16 -0400 Subject: FastCPU model added. It's very similar to the SimpleCPU, just without a lot of the stats tracking. Also various changes to make the CPU model less ISA dependent, which includes moving the code that checks for interrupts up to the ISA level, moving code that zeroes the zero registers up to the ISA level, and removing opcode and ra from the regfile. arch/alpha/alpha_memory.cc: The regfile has been changed so it no longer has the opcode and ra. Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA(). arch/alpha/ev5.cc: Moved code that once existed within simpleCPU to ev5, and templatized it. This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code. Also moved ISA specific zero registers from simpleCPU to here. arch/alpha/ev5.hh: Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile. arch/alpha/isa_desc: Added in declarations for the FastCPU model. arch/alpha/isa_traits.hh: Removed opcode and ra from the regfile. The xc now holds the actual instruction, and the opcode and ra can be obtained through it. Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0. arch/isa_parser.py: Added in FastCPUExecContext so it will generate code for the FastCPU model as well. cpu/exec_context.cc: Added in a more generic trap function so "ev5_trap" doesn't need to be called. It currently still calls the old method, with plans for making this ISA dependent in the future. cpu/exec_context.hh: Exec context now has the instruction within it. Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed. Also has declaration for more generic trap() function. cpu/simple_cpu/simple_cpu.cc: Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction. cpu/static_inst.hh: Added declaration for execute() using FastCPUExecContext. --HG-- extra : convert_revision : 0441ea3700ac50b733e485395d4dd4ac83666f92 --- arch/alpha/alpha_memory.cc | 4 +-- arch/alpha/ev5.cc | 67 ++++++++++++++++++++++++++++++++++++++++++++++ arch/alpha/ev5.hh | 2 ++ arch/alpha/isa_desc | 37 +++++++++++++++++++++++++ arch/alpha/isa_traits.hh | 10 +++++-- arch/isa_parser.py | 4 ++- 6 files changed, 119 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index 1608cc4a4..23815bf01 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -425,8 +425,8 @@ AlphaDTB::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const ipr[AlphaISA::IPR_VA] = vaddr; // set MM_STAT register flags - ipr[AlphaISA::IPR_MM_STAT] = (((xc->regs.opcode & 0x3f) << 11) - | ((xc->regs.ra & 0x1f) << 6) + ipr[AlphaISA::IPR_MM_STAT] = (((OPCODE(xc->getInst()) & 0x3f) << 11) + | ((RA(xc->getInst()) & 0x1f) << 6) | (flags & 0x3f)); // set VA_FORM register with faulting formatted address diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 9b3ac5fff..fe665abe6 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -6,6 +6,7 @@ #include "sim/debug.hh" #endif #include "cpu/exec_context.hh" +#include "cpu/fast_cpu/fast_cpu.hh" #include "sim/sim_events.hh" #include "targetarch/isa_traits.hh" #include "base/remote_gdb.hh" @@ -100,6 +101,64 @@ AlphaISA::initIPRs(RegFile *regs) } +template +void +AlphaISA::processInterrupts(XC *xc) +{ + //Check if there are any outstanding interrupts + //Handle the interrupts + int ipl = 0; + int summary = 0; + IntReg *ipr = xc->getIprPtr(); + + check_interrupts = 0; + + if (ipr[IPR_ASTRR]) + panic("asynchronous traps not implemented\n"); + + if (ipr[IPR_SIRR]) { + for (int i = INTLEVEL_SOFTWARE_MIN; + i < INTLEVEL_SOFTWARE_MAX; i++) { + if (ipr[IPR_SIRR] & (ULL(1) << i)) { + // See table 4-19 of the 21164 hardware reference + ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; + summary |= (ULL(1) << i); + } + } + } + + uint64_t interrupts = xc->intr_status(); + + if (interrupts) { + for (int i = INTLEVEL_EXTERNAL_MIN; + i < INTLEVEL_EXTERNAL_MAX; i++) { + if (interrupts & (ULL(1) << i)) { + // See table 4-19 of the 21164 hardware reference + ipl = i; + summary |= (ULL(1) << i); + } + } + } + + if (ipl && ipl > ipr[IPR_IPLR]) { + ipr[IPR_ISR] = summary; + ipr[IPR_INTID] = ipl; + xc->trap(Interrupt_Fault); + DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", + ipr[IPR_IPLR], ipl, summary); + } + +} + +template +void +AlphaISA::zeroRegisters(XC *xc) +{ + // Insure ISA semantics + xc->setIntReg(ZeroReg, 0); + xc->setFloatRegDouble(ZeroReg, 0.0); +} + void ExecContext::ev5_trap(Fault fault) { @@ -585,4 +644,12 @@ ExecContext::simPalCheck(int palFunc) return true; } +//Forward instantiation for FastCPU object +template +void AlphaISA::processInterrupts(FastCPU *xc); + +//Forward instantiation for FastCPU object +template +void AlphaISA::zeroRegisters(FastCPU *xc); + #endif // FULL_SYSTEM diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh index aa3d7e226..6947ef708 100644 --- a/arch/alpha/ev5.hh +++ b/arch/alpha/ev5.hh @@ -71,6 +71,8 @@ #define MM_STAT_ACV_MASK 0x0002 #define MM_STAT_WR_MASK 0x0001 +#define OPCODE(X) (X >> 26) & 0x3f +#define RA(X) (X >> 21) & 0x1f //////////////////////////////////////////////////////////////////////// // diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 0d1e7138f..016040b79 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -22,6 +22,7 @@ let {{ #include "base/misc.hh" #include "cpu/exec_context.hh" #include "cpu/exetrace.hh" +#include "cpu/fast_cpu/fast_cpu.hh" #include "cpu/full_cpu/dyn_inst.hh" #include "cpu/simple_cpu/simple_cpu.hh" #include "cpu/static_inst.hh" @@ -312,6 +313,9 @@ declare {{ Fault execute(SimpleCPUExecContext *, Trace::InstRecord *) { return No_Fault; } + Fault execute(FastCPUExecContext *, Trace::InstRecord *) + { return No_Fault; } + Fault execute(FullCPUExecContext *, Trace::InstRecord *) { return No_Fault; } }; @@ -719,6 +723,9 @@ declare {{ Fault execute(SimpleCPUExecContext *, Trace::InstRecord *) { panic("attempt to execute eacomp"); } + Fault execute(FastCPUExecContext *, Trace::InstRecord *) + { panic("attempt to execute eacomp"); } + Fault execute(FullCPUExecContext *, Trace::InstRecord *) { panic("attempt to execute eacomp"); } }; @@ -739,6 +746,9 @@ declare {{ Fault execute(SimpleCPUExecContext *, Trace::InstRecord *) { panic("attempt to execute memacc"); } + Fault execute(FastCPUExecContext *, Trace::InstRecord *) + { panic("attempt to execute memacc"); } + Fault execute(FullCPUExecContext *, Trace::InstRecord *) { panic("attempt to execute memacc"); } }; @@ -1452,6 +1462,14 @@ declare {{ return Unimplemented_Opcode_Fault; } + Fault execute(FastCPUExecContext *xc, + Trace::InstRecord *traceData) + { + panic("attempt to execute unimplemented instruction '%s' " + "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE); + return Unimplemented_Opcode_Fault; + } + Fault execute(FullCPUExecContext *xc, Trace::InstRecord *traceData) { @@ -1502,6 +1520,17 @@ declare {{ return No_Fault; } + Fault execute(FastCPUExecContext *xc, + Trace::InstRecord *traceData) + { + if (!warned) { + warn("instruction '%s' unimplemented\n", mnemonic); + warned = true; + } + + return No_Fault; + } + Fault execute(FullCPUExecContext *xc, Trace::InstRecord *traceData) { @@ -1573,6 +1602,14 @@ declare {{ return Unimplemented_Opcode_Fault; } + Fault execute(FastCPUExecContext *xc, + Trace::InstRecord *traceData) + { + panic("attempt to execute unknown instruction " + "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE); + return Unimplemented_Opcode_Fault; + } + Fault execute(FullCPUExecContext *xc, Trace::InstRecord *traceData) { diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 05ab89978..37ba77192 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -33,6 +33,7 @@ #include "targetarch/faults.hh" #include "base/misc.hh" +class FastCPU; class FullCPU; class Checkpoint; @@ -156,8 +157,6 @@ class AlphaISA int intrflag; // interrupt flag bool pal_shadow; // using pal_shadow registers #endif // FULL_SYSTEM - // Are these architectural, or just for convenience? - uint8_t opcode, ra; // current instruction details (for intr's) void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); @@ -233,6 +232,13 @@ class AlphaISA ConfigNode *node, RegFile ®s); #endif + + /** + * Function to insure ISA semantics about 0 registers. + * @param xc The execution context. + */ + template + static void zeroRegisters(XC *xc); }; diff --git a/arch/isa_parser.py b/arch/isa_parser.py index 0ee9e2e2d..cc42657e2 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -1387,6 +1387,7 @@ class InstObjParams: self.base_class = base_class self.exec_func_declarations = ''' Fault execute(SimpleCPUExecContext *, Trace::InstRecord *); + Fault execute(FastCPUExecContext *, Trace::InstRecord *); Fault execute(FullCPUExecContext *, Trace::InstRecord *); ''' if code_block: @@ -1433,7 +1434,8 @@ class InstObjParams: error(0, 'InstObjParams::subst: undefined template "%s"' % t) if template.find('%(cpu_model)') != -1: tmp = '' - for cpu_model in ('SimpleCPUExecContext', 'FullCPUExecContext'): + for cpu_model in ('SimpleCPUExecContext', 'FastCPUExecContext', + 'FullCPUExecContext'): self.cpu_model = cpu_model tmp += self._subst(template) result.append(tmp) -- cgit v1.2.3 From 6964ecd1cf14f294a300e91bc5b65042d03952d4 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 28 May 2004 14:42:59 -0400 Subject: Updated FastCPU model with all the recent changes. arch/alpha/ev5.cc: Updated to support new forms of setIntReg and setFloatRegDouble. Will need to be cleaned up in the future. arch/isa_parser.py: Added in FastCPU model. --HG-- extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db --- arch/alpha/ev5.cc | 6 ++++-- arch/isa_parser.py | 3 +++ 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index e88f6d0a3..ecf66f4f5 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -153,8 +153,10 @@ void AlphaISA::zeroRegisters(XC *xc) { // Insure ISA semantics - xc->setIntReg(ZeroReg, 0); - xc->setFloatRegDouble(ZeroReg, 0.0); + // (no longer very clean due to the change in setIntReg() in the + // cpu model. Consider changing later.) + xc->xc->setIntReg(ZeroReg, 0); + xc->xc->setFloatRegDouble(ZeroReg, 0.0); } void diff --git a/arch/isa_parser.py b/arch/isa_parser.py index 7f77241be..c808c2565 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -630,6 +630,9 @@ class CpuModel: CpuModel('SimpleCPU', 'simple_cpu_exec.cc', '#include "cpu/simple_cpu/simple_cpu.hh"', { 'CPU_exec_context': 'SimpleCPU' }) +CpuModel('FastCPU', 'fast_cpu_exec.cc', + '#include "cpu/fast_cpu/fast_cpu.hh"', + { 'CPU_exec_context': 'FastCPU' }) CpuModel('FullCPU', 'full_cpu_exec.cc', '#include "cpu/full_cpu/dyn_inst.hh"', { 'CPU_exec_context': 'DynInst' }) -- cgit v1.2.3