From 524da7cd20dae5416cd0962a9b9bd49dcf92ee51 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 8 Feb 2006 10:40:43 -0500 Subject: Replace ad-hoc or locally defined power-of-2 tests with isPowerOf2() from intmath.hh. base/sched_list.hh: Use isPowerOf2() from intmath.hh. --HG-- extra : convert_revision : 7b2409531d8ed194aa7e1cfcd1ecb8460c797a16 --- base/sched_list.hh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'base') diff --git a/base/sched_list.hh b/base/sched_list.hh index 0e2f3ddcb..f794e3514 100644 --- a/base/sched_list.hh +++ b/base/sched_list.hh @@ -30,8 +30,10 @@ #define SCHED_LIST_HH #include +#include "base/intmath.hh" #include "base/misc.hh" + // Any types you use this class for must be covered here... namespace { void ClearEntry(int &i) { i = 0; }; @@ -80,7 +82,7 @@ SchedList::SchedList(unsigned _size) size = _size; // size must be a power of two - if (size & (size-1)) { + if (!isPowerOf2(size)) { panic("SchedList: size must be a power of two"); } -- cgit v1.2.3 From fb7899aa681001d2af7837eae7bf0e19fd3e1b02 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 10 Feb 2006 14:21:32 -0500 Subject: fix problems on darwin/*BSD for syscall emulation mode arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: fixup for bsd hosts. Some headers are included by default which means that more variables need TGT_ prefixes and there isn't a stat call (everything is a stat64 call) so we have to work around that a bit base/intmath.hh: base/socket.cc: this is no longer needed with mac os 10.4 cpu/inst_seq.hh: just use a uint64_t instead of long long cpu/o3/inst_queue_impl.hh: I much cleaner way to get max int sim/syscall_emul.hh: fix stat64 problems on *BSD --HG-- extra : convert_revision : 9eef5f896e083ae1774e818a9765dd83e0305942 --- base/intmath.hh | 16 ---------------- base/socket.cc | 3 --- 2 files changed, 19 deletions(-) (limited to 'base') diff --git a/base/intmath.hh b/base/intmath.hh index c8b9c5ec5..df0687c62 100644 --- a/base/intmath.hh +++ b/base/intmath.hh @@ -145,22 +145,6 @@ floorLog2(long long x) return floorLog2((unsigned long long)x); } -#if defined(__APPLE__) -inline int -floorLog2(size_t x) -{ - assert(x > 0); - assert(sizeof(size_t) == 4 || sizeof(size_t) == 8); - - // It's my hope that this is optimized away? - if (sizeof(size_t) == 4) - return floorLog2((uint32_t)x); - else if (sizeof(size_t) == 8) - return floorLog2((uint64_t)x); - -} -#endif - template inline int ceilLog2(T n) diff --git a/base/socket.cc b/base/socket.cc index f33e79426..45a60e7e3 100644 --- a/base/socket.cc +++ b/base/socket.cc @@ -93,9 +93,6 @@ ListenSocket::listen(int port, bool reuse) return true; } -#if defined(__APPLE__) -typedef int socklen_t; -#endif // Open a connection. Accept will block, so if you don't want it to, // make sure a connection is ready before you call accept. -- cgit v1.2.3 From 2c5e03550adcd1348cc1d6f3c00af77cbf99c5ce Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 12 Feb 2006 12:40:58 -0500 Subject: Removed isa_traits.hh from targetarch, moved vptr.hh from arch/alpha to sim, fixed an include to have the new location, and removed an ambiguating function declaration in byteswap.hh. SConscript: Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh targetarch/isa_traits.hh is now included through arch/isa_traits.hh vptr.hh was removed from targetarch, and moved to sim arch/alpha/pseudo_inst.cc: Moved vptr.hh from targetarch to sim base/loader/object_file.hh: base/loader/symtab.hh: cpu/base.hh: dev/ide_disk.cc: Changed the include of isa_traits.hh from targetarch to arch cpu/static_inst.hh: dev/platform.hh: dev/simple_disk.hh: kern/tru64/dump_mbuf.cc: kern/tru64/mbuf.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/process.hh: sim/syscall_emul.hh: Changed the include of isa_traits.hh from targetarch to arch. kern/linux/linux_threadinfo.hh: Changed the include of vptr.hh from targetarch to sim. sim/byteswap.hh: Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t) sim/vptr.hh: Fixed the assert in the equals operator. Changed the AlphaISA namespace reference to TheISA. Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures. Added an include of arch/isa_traits.hh so that TheISA would be defined. --HG-- extra : convert_revision : e3c6ac17ed0277cfeba1d35cd63eba66eba5996f --- base/loader/object_file.hh | 2 +- base/loader/symtab.hh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'base') diff --git a/base/loader/object_file.hh b/base/loader/object_file.hh index 26d3ef3b0..3c8659e18 100644 --- a/base/loader/object_file.hh +++ b/base/loader/object_file.hh @@ -29,7 +29,7 @@ #ifndef __OBJECT_FILE_HH__ #define __OBJECT_FILE_HH__ -#include "targetarch/isa_traits.hh" // for Addr +#include "arch/isa_traits.hh" // for Addr class FunctionalMemory; class SymbolTable; diff --git a/base/loader/symtab.hh b/base/loader/symtab.hh index 324fd8b45..ebcda1345 100644 --- a/base/loader/symtab.hh +++ b/base/loader/symtab.hh @@ -32,7 +32,7 @@ #include #include -#include "targetarch/isa_traits.hh" // for Addr +#include "arch/isa_traits.hh" // for Addr class Checkpoint; class SymbolTable -- cgit v1.2.3 From 463aa6d49d49ba9c383f07207df57bad75c58ec9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 19 Feb 2006 02:34:37 -0500 Subject: Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. arch/alpha/alpha_linux_process.cc: Added using directive for AlphaISA namespace arch/alpha/alpha_memory.hh: arch/alpha/isa/branch.isa: cpu/pc_event.hh: Added typedefs for Addr arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: Added using directive for AlphaISA arch/alpha/ev5.hh: Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace. arch/alpha/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/alpha/isa/main.isa: Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh arch/alpha/isa/mem.isa: Untemplatized StaticInst and StaticInstPtr arch/alpha/isa/pal.isa: cpu/base_dyn_inst.cc: Untemplatized StaticInstPtr arch/alpha/isa_traits.hh: Changed variables to be externs instead of static since they are part of a namespace and not a class. arch/alpha/stacktrace.cc: Untemplatized StaticInstPtr, and added a using directive for AlphaISA. arch/alpha/stacktrace.hh: Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr arch/alpha/vtophys.cc: Added a using directive for AlphaISA arch/alpha/vtophys.hh: Added the AlphaISA namespace specifier where needed arch/isa_parser.py: Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace. base/loader/object_file.hh: cpu/o3/bpred_unit.hh: Added a typedef for Addr base/loader/symtab.hh: Added a typedef for Addr, and added a TheISA to Addr in another typedef base/remote_gdb.cc: Added a using namespace TheISA, and untemplatized StaticInstPtr base/remote_gdb.hh: Added typedefs for Addr and MachInst cpu/base.cc: Added TheISA specifier to some variables exported from the isa. cpu/base.hh: Added a typedef for Addr, and TheISA to some variables from the ISA cpu/base_dyn_inst.hh: Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA. cpu/exec_context.hh: Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa cpu/exetrace.hh: Added typedefs for some types from the ISA, and untemplatized StaticInstPtr cpu/memtest/memtest.cc: cpu/o3/btb.cc: dev/baddev.cc: dev/ide_ctrl.cc: dev/ide_disk.cc: dev/isa_fake.cc: dev/ns_gige.cc: dev/pciconfigall.cc: dev/platform.cc: dev/sinic.cc: dev/uart8250.cc: kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/system_events.cc: kern/tru64/dump_mbuf.cc: kern/tru64/tru64_events.cc: sim/process.cc: sim/pseudo_inst.cc: sim/system.cc: Added using namespace TheISA cpu/memtest/memtest.hh: cpu/trace/opt_cpu.hh: cpu/trace/reader/itx_reader.hh: dev/ide_disk.hh: dev/pcidev.hh: dev/platform.hh: dev/tsunami.hh: sim/system.hh: sim/vptr.hh: Added typedef for Addr cpu/o3/2bit_local_pred.hh: Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr cpu/o3/alpha_cpu.hh: Added typedefs for Addr and IntReg cpu/o3/alpha_cpu_impl.hh: Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed. cpu/o3/alpha_dyn_inst.hh: Cleaned up some typedefs, and untemplatized StaticInst cpu/o3/alpha_dyn_inst_impl.hh: untemplatized StaticInstPtr cpu/o3/alpha_impl.hh: Fixed up a typedef of MachInst cpu/o3/bpred_unit_impl.hh: Added a using TheISA::MachInst to a function cpu/o3/btb.hh: Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr cpu/o3/commit.hh: Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now. cpu/o3/cpu.cc: Cleaned up namespace issues cpu/o3/cpu.hh: Cleaned up namespace usage cpu/o3/decode.hh: Removed typedef of ISA, and changed it to TheISA cpu/o3/fetch.hh: Fized up typedefs, and changed ISA to TheISA cpu/o3/free_list.hh: Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh cpu/o3/iew.hh: Removed typedef of ISA cpu/o3/iew_impl.hh: Added TheISA namespace specifier to MachInst cpu/o3/ras.hh: Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr. cpu/o3/regfile.hh: Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile cpu/o3/rename.hh: Changed ISA to TheISA, and added a typedef for RegIndex cpu/o3/rename_map.hh: Added an include for arch/isa_traits.hh, and a typedef for RegIndex cpu/o3/rob.hh: Added a typedef for RegIndex cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr cpu/ozone/cpu.hh: Changed ISA into TheISA, and untemplatized StaticInst cpu/pc_event.cc: Added namespace specifier TheISA to Addr types cpu/profile.hh: kern/kernel_stats.hh: Added typedef for Addr, and untemplatized StaticInstPtr cpu/simple/cpu.cc: Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst cpu/simple/cpu.hh: Added a typedef for MachInst, and untemplatized StaticInst cpu/static_inst.cc: Untemplatized StaticInst cpu/static_inst.hh: Untemplatized StaticInst by using the TheISA namespace dev/alpha_console.cc: Added using namespace AlphaISA dev/simple_disk.hh: Added typedef for Addr and fixed up some formatting dev/sinicreg.hh: Added TheISA namespace specifier where needed dev/tsunami.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Added using namespace TheISA. It might be better for it to be AlphaISA dev/tsunami_cchip.cc: Added typedef for TheISA. It might be better for it to be AlphaISA kern/linux/aligned.hh: sim/pseudo_inst.hh: Added TheISA namespace specifier to Addr kern/linux/linux_threadinfo.hh: Added typedef for Addr, and TheISA namespace specifier to StackPointerReg kern/tru64/mbuf.hh: Added TheISA to Addr type in structs sim/process.hh: Added typedefs of Addr, RegFile, and MachInst sim/syscall_emul.cc: Added using namespace TheISA, and a cast of VMPageSize to the int type sim/syscall_emul.hh: Added typecast for Addr, and TheISA namespace specifier for where needed --HG-- extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45 --- base/loader/object_file.hh | 1 + base/loader/symtab.hh | 3 ++- base/remote_gdb.cc | 3 ++- base/remote_gdb.hh | 3 +++ 4 files changed, 8 insertions(+), 2 deletions(-) (limited to 'base') diff --git a/base/loader/object_file.hh b/base/loader/object_file.hh index 3c8659e18..e90f93847 100644 --- a/base/loader/object_file.hh +++ b/base/loader/object_file.hh @@ -37,6 +37,7 @@ class SymbolTable; class ObjectFile { public: + typedef TheISA::Addr Addr; enum Arch { UnknownArch, diff --git a/base/loader/symtab.hh b/base/loader/symtab.hh index ebcda1345..38b4cdee2 100644 --- a/base/loader/symtab.hh +++ b/base/loader/symtab.hh @@ -37,8 +37,9 @@ class Checkpoint; class SymbolTable { + typedef TheISA::Addr Addr; public: - typedef std::map ATable; + typedef std::map ATable; typedef std::map STable; private: diff --git a/base/remote_gdb.cc b/base/remote_gdb.cc index 67d745d43..17ec21fed 100644 --- a/base/remote_gdb.cc +++ b/base/remote_gdb.cc @@ -132,6 +132,7 @@ #include "targetarch/vtophys.hh" using namespace std; +using namespace TheISA; #ifndef NDEBUG vector debuggers; @@ -494,7 +495,7 @@ RemoteGDB::setSingleStep() // User was stopped at pc, e.g. the instruction at pc was not // executed. MachInst inst = read(pc); - StaticInstPtr si(inst); + StaticInstPtr si(inst); if (si->hasBranchTarget(pc, context, bpc)) { // Don't bother setting a breakpoint on the taken branch if it // is the same as the next pc diff --git a/base/remote_gdb.hh b/base/remote_gdb.hh index 652a58317..126d5f6f8 100644 --- a/base/remote_gdb.hh +++ b/base/remote_gdb.hh @@ -43,6 +43,9 @@ class PhysicalMemory; class GDBListener; class RemoteGDB { + protected: + typedef TheISA::Addr Addr; + typedef TheISA::MachInst MachInst; private: friend void debugger(); friend class GDBListener; -- cgit v1.2.3 From 3f7979c99d8dc4f434e3daa2e179616f1669e16e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 21 Feb 2006 03:38:21 -0500 Subject: Made Addr a global type --HG-- extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835 --- base/loader/object_file.hh | 1 - base/loader/symtab.hh | 3 +-- base/remote_gdb.hh | 1 - 3 files changed, 1 insertion(+), 4 deletions(-) (limited to 'base') diff --git a/base/loader/object_file.hh b/base/loader/object_file.hh index e90f93847..3c8659e18 100644 --- a/base/loader/object_file.hh +++ b/base/loader/object_file.hh @@ -37,7 +37,6 @@ class SymbolTable; class ObjectFile { public: - typedef TheISA::Addr Addr; enum Arch { UnknownArch, diff --git a/base/loader/symtab.hh b/base/loader/symtab.hh index 38b4cdee2..ebcda1345 100644 --- a/base/loader/symtab.hh +++ b/base/loader/symtab.hh @@ -37,9 +37,8 @@ class Checkpoint; class SymbolTable { - typedef TheISA::Addr Addr; public: - typedef std::map ATable; + typedef std::map ATable; typedef std::map STable; private: diff --git a/base/remote_gdb.hh b/base/remote_gdb.hh index 126d5f6f8..b7abf5116 100644 --- a/base/remote_gdb.hh +++ b/base/remote_gdb.hh @@ -44,7 +44,6 @@ class GDBListener; class RemoteGDB { protected: - typedef TheISA::Addr Addr; typedef TheISA::MachInst MachInst; private: friend void debugger(); -- cgit v1.2.3 From 08637efadc40a1003d68bba91dedb007fe10798c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 24 Feb 2006 01:51:45 -0500 Subject: Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type. arch/alpha/alpha_memory.cc: arch/alpha/isa/decoder.isa: Added news where faults are created. arch/alpha/ev5.cc: Changed places where a fault was compared to a fault type to use isA rather than == arch/alpha/faults.cc: arch/alpha/faults.hh: Changed Fault to be a RefCountingPtr arch/alpha/isa/fp.isa: Added a new where a FloatEnableFault was created. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: Added a new where an UnimplementedFault is created. base/refcnt.hh: Added include of stddef.h for the NULL macro cpu/base_dyn_inst.cc: Added a new where an UnimplementedOpcodeFault is created. cpu/o3/alpha_cpu_impl.hh: Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name() cpu/o3/regfile.hh: Added new where UnimplementedOpcodeFaults are created. cpu/simple/cpu.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created. dev/alpha_console.cc: Added news where MachineCheckFaults are created. dev/pcidev.hh: Added news where MachineCheckFaults are generated. dev/sinic.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables. kern/kernel_stats.cc: Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future. kern/kernel_stats.hh: Commented out the declaration of _fault. when fault() is called, the fault increments its own stat. sim/faults.cc: sim/faults.hh: Changed Fault from a FaultBase * to a RefCountingPtr. --HG-- extra : convert_revision : b40ccfc42482d5a115e111dd897fa378d23c6c7d --- base/refcnt.hh | 2 ++ 1 file changed, 2 insertions(+) (limited to 'base') diff --git a/base/refcnt.hh b/base/refcnt.hh index 9d9ed4337..de589f7c5 100644 --- a/base/refcnt.hh +++ b/base/refcnt.hh @@ -29,6 +29,8 @@ #ifndef __REFCNT_HH__ #define __REFCNT_HH__ +#include //For the NULL macro definition + class RefCounted { private: -- cgit v1.2.3 From c5dcd152f264a837f50d39f98d0f4f81478e3553 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 27 Feb 2006 05:35:43 -0500 Subject: Changed targetarch to just arch. SConscript: Changed all of the "targetarch" files to be "arch" files arch/SConscript: Added all of the remaining targetarch files to isa_switch_hdrs --HG-- extra : convert_revision : a37d18349e27cf92dce12814f21944daa7fe9480 --- base/loader/exec_aout.h | 2 +- base/loader/exec_ecoff.h | 2 +- base/remote_gdb.cc | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'base') diff --git a/base/loader/exec_aout.h b/base/loader/exec_aout.h index 76ebe9bb5..3863a92fb 100644 --- a/base/loader/exec_aout.h +++ b/base/loader/exec_aout.h @@ -55,6 +55,6 @@ (N_GETMAGIC(ex) != NMAGIC && N_GETMAGIC(ex) != OMAGIC && \ N_GETMAGIC(ex) != ZMAGIC) -#include "targetarch/aout_machdep.h" +#include "arch/aout_machdep.h" #endif /* !_SYS_EXEC_AOUT_H_ */ diff --git a/base/loader/exec_ecoff.h b/base/loader/exec_ecoff.h index 4eece4318..79cd22a6e 100644 --- a/base/loader/exec_ecoff.h +++ b/base/loader/exec_ecoff.h @@ -37,7 +37,7 @@ #ifndef _SYS_EXEC_ECOFF_H_ #define _SYS_EXEC_ECOFF_H_ -#include "targetarch/ecoff_machdep.h" +#include "arch/ecoff_machdep.h" struct ecoff_filehdr { coff_ushort f_magic; /* magic number */ diff --git a/base/remote_gdb.cc b/base/remote_gdb.cc index 17ec21fed..24280244f 100644 --- a/base/remote_gdb.cc +++ b/base/remote_gdb.cc @@ -129,7 +129,7 @@ #include "cpu/static_inst.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" using namespace std; using namespace TheISA; -- cgit v1.2.3 From 70b35bab5778799805fe9b6040b23eb1885dbfc3 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Mon, 27 Feb 2006 11:44:35 -0500 Subject: Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs. They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future). arch/alpha/alpha_memory.cc: Change accesses to IPR to go through the XC. arch/alpha/ev5.cc: Change accesses for IPRs to go through the misc regs. arch/alpha/isa/decoder.isa: Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect(). arch/alpha/isa/fp.isa: Change accesses to IPRs and Fpcr to go through the misc regs. arch/alpha/isa/main.isa: Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index. arch/alpha/isa_traits.hh: Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs. Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes. The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs. arch/alpha/stacktrace.cc: cpu/simple/cpu.cc: dev/sinic.cc: Change accesses to the IPRs to go through the XC. arch/alpha/vtophys.cc: Change access to the IPR to go through the XC. arch/isa_parser.py: Change generation of code for control registers to use the readMiscReg and setMiscReg functions. base/remote_gdb.cc: Change accesses to the IPR to go through the XC. cpu/exec_context.hh: Use the miscRegs to access the lock addr, lock flag, and other misc registers. cpu/o3/alpha_cpu.hh: cpu/simple/cpu.hh: Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions. cpu/o3/alpha_cpu_impl.hh: Change accesses to the IPRs to go through the miscRegs. For now comment out some of the accesses to the misc regs until the proxy exec context is completed. cpu/o3/alpha_dyn_inst.hh: Change accesses to misc regs to use readMiscReg and setMiscReg. cpu/o3/alpha_dyn_inst_impl.hh: Remove old misc reg accessors. cpu/o3/cpu.cc: Comment out old misc reg accesses until the proxy exec context is completed. cpu/o3/cpu.hh: Change accesses to the misc regs. cpu/o3/regfile.hh: Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed. kern/kernel_stats.cc: kern/system_events.cc: Have accesses to the IPRs go through the XC. kern/tru64/tru64.hh: Have accesses to the misc regs use the new access methods. --HG-- extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76 --- base/remote_gdb.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'base') diff --git a/base/remote_gdb.cc b/base/remote_gdb.cc index 17ec21fed..5f1a2db2c 100644 --- a/base/remote_gdb.cc +++ b/base/remote_gdb.cc @@ -371,7 +371,7 @@ RemoteGDB::acc(Addr va, size_t len) if (AlphaISA::PcPAL(va) || va < 0x10000) return true; - Addr ptbr = context->regs.ipr[AlphaISA::IPR_PALtemp20]; + Addr ptbr = context->readMiscReg(AlphaISA::IPR_PALtemp20); TheISA::PageTableEntry pte = kernel_pte_lookup(pmem, ptbr, va); if (!pte.valid()) { DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va); -- cgit v1.2.3 From e7825aab59e03b9691d361338fba222f56446f77 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 3 Mar 2006 15:28:25 -0500 Subject: Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included. The shadow registers are folded into the normal integer registers to ease renaming indexing. Include the removed Opcdec class of instructions for faulting when a pal mode only instruction is decoded in non-pal mode. arch/alpha/ev5.cc: Changes to automatically map the shadow registers if the instruction is in PAL mode. arch/alpha/isa/branch.isa: arch/alpha/isa/decoder.isa: arch/alpha/isa/fp.isa: arch/alpha/isa/int.isa: arch/alpha/isa/mem.isa: arch/alpha/isa/pal.isa: arch/alpha/isa/unimp.isa: Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits. arch/alpha/isa/main.isa: Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits. The decoder (for Alpha) uses the 32nd bit in order to determine if the machine is in PAL mode. If it is, then it refers to the reg_redir table to determine the true index of the register it is using. Also include the opcdec instruction definition. arch/alpha/isa_traits.hh: Define ExtMachInst type that is used by the static inst in order to decode the instruction, given the context of being in pal mode or not. Redefine the number of Int registers, splitting it into NumIntArchRegs (32) and NumIntRegs (32 + 8 shadow registers). Change the dependence tags to reflect the integer registers include the 8 shadow registers. Define function to make an ExtMachInst. Currently it is somewhat specific to Alpha; in the future it must be decided to make this more generic and possibly slower, or leave it specific to each architecture and ifdef it within the CPU. arch/isa_parser.py: Have static insts decode on the ExtMachInst. base/remote_gdb.cc: Support the automatic remapping of shadow registers. Remote GDB must now look at the PC being read in order to tell if it should use the normal register indices or the shadow register indices. cpu/o3/regfile.hh: Comment out the pal registers; they are now a part of the integer registers. cpu/simple/cpu.cc: Create an ExtMachInst to decode on, based on the normal MachInst and the PC of the instructoin. cpu/static_inst.hh: Change from MachInst to ExtMachInst to support shadow register renaming. --HG-- extra : convert_revision : 1d23eabf735e297068e1917445a6348e9f8c88d5 --- base/remote_gdb.cc | 39 +++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) (limited to 'base') diff --git a/base/remote_gdb.cc b/base/remote_gdb.cc index f56ddf7cf..57a179719 100644 --- a/base/remote_gdb.cc +++ b/base/remote_gdb.cc @@ -424,12 +424,25 @@ void RemoteGDB::getregs() { memset(gdbregs, 0, sizeof(gdbregs)); - memcpy(&gdbregs[KGDB_REG_V0], context->regs.intRegFile, 32 * sizeof(uint64_t)); + + gdbregs[KGDB_REG_PC] = context->readPC(); + + // @todo: Currently this is very Alpha specific. + if (AlphaISA::PcPAL(gdbregs[KGDB_REG_PC])) { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + gdbregs[i] = context->readIntReg(AlphaISA::reg_redir[i]); + } + } else { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + gdbregs[i] = context->readIntReg(i); + } + } + #ifdef KGDB_FP_REGS - memcpy(&gdbregs[KGDB_REG_F0], context->regs.floatRegFile.q, - 32 * sizeof(uint64_t)); + for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) { + gdbregs[i + KGDB_REG_F0] = context->readFloatRegInt(i); + } #endif - gdbregs[KGDB_REG_PC] = context->regs.pc; } /////////////////////////////////////////////////////////// @@ -441,11 +454,21 @@ RemoteGDB::getregs() void RemoteGDB::setregs() { - memcpy(context->regs.intRegFile, &gdbregs[KGDB_REG_V0], - 32 * sizeof(uint64_t)); + // @todo: Currently this is very Alpha specific. + if (AlphaISA::PcPAL(gdbregs[KGDB_REG_PC])) { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + context->setIntReg(AlphaISA::reg_redir[i], gdbregs[i]); + } + } else { + for (int i = 0; i < TheISA::NumIntArchRegs; ++i) { + context->setIntReg(i, gdbregs[i]); + } + } + #ifdef KGDB_FP_REGS - memcpy(context->regs.floatRegFile.q, &gdbregs[KGDB_REG_F0], - 32 * sizeof(uint64_t)); + for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) { + context->setFloatRegInt(i, gdbregs[i + KGDB_REG_F0]); + } #endif context->regs.pc = gdbregs[KGDB_REG_PC]; } -- cgit v1.2.3 From 7c4c623302dca7da95b1c95d4968f4ef76de391d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 4 Mar 2006 03:09:23 -0500 Subject: Filled out the object file loader so it can load object files for several OSs and architectures. SConscript: Added ./libelf as an include search directory. There might be a better spot for this than where I put it. arch/SConscript: Combined the linux_process.h and tru64_process.h into process.h. This allows each ISA to support processes from arbitrary OSs. arch/alpha/SConscript: Added process.cc as a source file. It provides an implementation of createProcess, which takes an object_file object and creates the appropriate process object, or dies. base/loader/elf_object.cc: Actually extract the OS and architecture from the elf file, rather than always guessing Alpha and Linux. base/loader/object_file.hh: Added constants for SPARC, MIPS, and Solaris, and changed the include for the Addr type. sim/process.cc: Pushed creation of specific process objects into the ISA specific code. --HG-- extra : convert_revision : b4754e7ca8328672d07e1394c4d162e199606b53 --- base/loader/elf_object.cc | 45 +++++++++++++++++++++++++++++++++++++++++---- base/loader/object_file.hh | 11 ++++++++--- 2 files changed, 49 insertions(+), 7 deletions(-) (limited to 'base') diff --git a/base/loader/elf_object.cc b/base/loader/elf_object.cc index b74d537af..9dd9f9d00 100644 --- a/base/loader/elf_object.cc +++ b/base/loader/elf_object.cc @@ -56,6 +56,8 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data) { Elf *elf; GElf_Ehdr ehdr; + Arch arch = UnknownArch; + OpSys opSys = UnknownOpSys; // check that header matches library version if (elf_version(EV_CURRENT) == EV_NONE) @@ -73,8 +75,8 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data) return NULL; } else { - if (ehdr.e_ident[EI_CLASS] == ELFCLASS32) - panic("32 bit ELF Binary, Not Supported"); +// if (ehdr.e_ident[EI_CLASS] == ELFCLASS32) +// panic("32 bit ELF Binary, Not Supported"); /* @todo this emachine value isn't offical yet. * so we probably shouldn't check it. */ // if (ehdr.e_machine != EM_ALPHA) @@ -82,8 +84,43 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data) elf_end(elf); - return new ElfObject(fname, fd, len, data, - ObjectFile::Alpha, ObjectFile::Linux); + //Detect the architecture + //Versioning issues in libelf need to be resolved to get the correct + //SPARC constants. + //If MIPS supports 32 bit executables, this may need to be changed. + //Also, there are other MIPS constants which may be used, like + //EM_MIPS_RS3_LE and EM_MIPS_X + //Since we don't know how to check for alpha right now, we'll + //just assume if it wasn't something else and it's 64 bit, that's + //what it must be. + if (ehdr.e_machine == EM_SPARC64 || + ehdr.e_machine == EM_SPARC || + ehdr.e_machine == EM_SPARCV9) { + arch = ObjectFile::SPARC; + } else if (ehdr.e_machine == EM_MIPS + && ehdr.e_ident[EI_CLASS] == ELFCLASS32) { + arch = ObjectFile::MIPS; + } else if (ehdr.e_ident[EI_CLASS] == ELFCLASS64) { + arch = ObjectFile::Alpha; + } else { + arch = ObjectFile::UnknownArch; + } + + //Detect the operating system + switch (ehdr.e_ident[EI_OSABI]) + { + case ELFOSABI_LINUX: + opSys = ObjectFile::Linux; + break; + case ELFOSABI_SOLARIS: + opSys = ObjectFile::Solaris; + case ELFOSABI_TRU64: + opSys = ObjectFile::Tru64; + default: + opSys = ObjectFile::UnknownOpSys; + } + + return new ElfObject(fname, fd, len, data, arch, opSys); } } diff --git a/base/loader/object_file.hh b/base/loader/object_file.hh index 3c8659e18..1b44ae14f 100644 --- a/base/loader/object_file.hh +++ b/base/loader/object_file.hh @@ -29,7 +29,9 @@ #ifndef __OBJECT_FILE_HH__ #define __OBJECT_FILE_HH__ -#include "arch/isa_traits.hh" // for Addr +#include + +#include "sim/host.hh" // for Addr class FunctionalMemory; class SymbolTable; @@ -40,13 +42,16 @@ class ObjectFile enum Arch { UnknownArch, - Alpha + Alpha, + SPARC, + MIPS }; enum OpSys { UnknownOpSys, Tru64, - Linux + Linux, + Solaris }; protected: -- cgit v1.2.3 From 1e071c9f5fd5258ff92dc496aecc175db94a5ad7 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sat, 4 Mar 2006 12:35:13 -0500 Subject: we REALLY don't want to use system headers for libelf... use "" not <> targetarch->arch arch/alpha/system.cc: targetarch -> arch base/loader/elf_object.cc: we REALLY don't want to use system headers for libelf... use "" not <> --HG-- extra : convert_revision : d0e1672dc655dca3081e36b2158e7b19ef54af40 --- base/loader/elf_object.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'base') diff --git a/base/loader/elf_object.cc b/base/loader/elf_object.cc index 9dd9f9d00..fd69c9e56 100644 --- a/base/loader/elf_object.cc +++ b/base/loader/elf_object.cc @@ -38,8 +38,8 @@ #define __LIBELF_NEED_LINK_H 0 #define __LIBELF_SYMBOL_VERSIONS 0 -#include -#include +#include "libelf/libelf.h" +#include "libelf/gelf.h" #include "base/loader/elf_object.hh" -- cgit v1.2.3 From f15e492375e8ecd42a1f0ba7ead68cfeb2b4b673 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sat, 4 Mar 2006 15:18:40 -0500 Subject: Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. The major change is renaming the old ExecContext to CPUExecContext, and creating two new classes, ExecContext (an abstract class), and ProxyExecContext (a templated class that derives from ExecContext). Code outside of the CPU continues to use ExecContext as normal (other than not being able to access variables within the XC). The CPU uses the CPUExecContext, or however else it stores its own state. It then creates a ProxyExecContext, templated on the class used to hold its state. This proxy is passed to any code outside of the CPU that needs to access the XC. This allows code outside of the CPU to use the ExecContext interface to access any state needed, without knowledge of how that state is laid out. Note that these changes will not compile without the accompanying revision to automatically rename the shadow registers. SConscript: Include new file, cpu_exec_context.cc. arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_memory.cc: arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: arch/alpha/isa/decoder.isa: arch/alpha/stacktrace.cc: arch/alpha/vtophys.cc: base/remote_gdb.cc: cpu/intr_control.cc: Avoid directly accessing objects within the XC. arch/alpha/ev5.cc: Avoid directly accessing objects within the XC. KernelStats have been moved to the BaseCPU instead of the XC. arch/alpha/isa_traits.hh: Remove clearIprs(). It wasn't used very often and it did not work well with the proxy ExecContext. cpu/base.cc: Place kernel stats within the BaseCPU instead of the ExecContext. For now comment out the profiling code sampling until its exact location is decided upon. cpu/base.hh: Kernel stats are now in the BaseCPU instead of the ExecContext. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details. cpu/exetrace.cc: Remove unneeded include of exec_context.hh. cpu/intr_control.hh: cpu/o3/alpha_cpu_builder.cc: Remove unneeded include of exec_context.hh cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details. Also avoid accessing anything directly from the XC. cpu/pc_event.cc: Avoid accessing objects directly from the XC. dev/tsunami_cchip.cc: Avoid accessing objects directly within the XC> kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/linux/linux_threadinfo.hh: kern/tru64/dump_mbuf.cc: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: sim/syscall_emul.cc: sim/syscall_emul.hh: Avoid accessing objects directly within the XC. kern/kernel_stats.cc: kern/kernel_stats.hh: Kernel stats no longer exist within the XC. kern/system_events.cc: Avoid accessing objects directly within the XC. Also kernel stats are now in the BaseCPU. sim/process.cc: sim/process.hh: Avoid accessing regs directly within an ExecContext. Instead use a CPUExecContext to initialize the registers and copy them over. cpu/cpu_exec_context.cc: Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU. cpu/cpu_exec_context.hh: Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU. Remove kernel stats from the ExecContext. sim/pseudo_inst.cc: Kernel stats now live within the CPU. Avoid accessing objects directly within the XC. --HG-- rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : a75393a8945c80cca225b5e9d9c22a16609efb85 --- base/remote_gdb.cc | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'base') diff --git a/base/remote_gdb.cc b/base/remote_gdb.cc index 5f1a2db2c..50c4798c4 100644 --- a/base/remote_gdb.cc +++ b/base/remote_gdb.cc @@ -429,7 +429,7 @@ RemoteGDB::getregs() memcpy(&gdbregs[KGDB_REG_F0], context->regs.floatRegFile.q, 32 * sizeof(uint64_t)); #endif - gdbregs[KGDB_REG_PC] = context->regs.pc; + gdbregs[KGDB_REG_PC] = context->readPC(); } /////////////////////////////////////////////////////////// @@ -447,7 +447,7 @@ RemoteGDB::setregs() memcpy(context->regs.floatRegFile.q, &gdbregs[KGDB_REG_F0], 32 * sizeof(uint64_t)); #endif - context->regs.pc = gdbregs[KGDB_REG_PC]; + context->setPC(gdbregs[KGDB_REG_PC]); } void @@ -486,7 +486,7 @@ RemoteGDB::clearSingleStep() void RemoteGDB::setSingleStep() { - Addr pc = context->regs.pc; + Addr pc = context->readPC(); Addr npc, bpc; bool set_bt = false; @@ -835,7 +835,7 @@ RemoteGDB::trap(int type) return false; DPRINTF(GDBMisc, "trap: PC=%#x NPC=%#x\n", - context->regs.pc, context->regs.npc); + context->readPC(), context->readNextPC()); clearSingleStep(); @@ -990,8 +990,8 @@ RemoteGDB::trap(int type) subcmd = hex2i(&p); if (*p++ == ';') { val = hex2i(&p); - context->regs.pc = val; - context->regs.npc = val + sizeof(MachInst); + context->setPC(val); + context->setNextPC(val + sizeof(MachInst)); } clearSingleStep(); goto out; @@ -999,8 +999,8 @@ RemoteGDB::trap(int type) case KGDB_CONT: if (p - data < datalen) { val = hex2i(&p); - context->regs.pc = val; - context->regs.npc = val + sizeof(MachInst); + context->setPC(val); + context->setNextPC(val + sizeof(MachInst)); } clearSingleStep(); goto out; @@ -1009,8 +1009,8 @@ RemoteGDB::trap(int type) subcmd = hex2i(&p); if (*p++ == ';') { val = hex2i(&p); - context->regs.pc = val; - context->regs.npc = val + sizeof(MachInst); + context->setPC(val); + context->setNextPC(val + sizeof(MachInst)); } setSingleStep(); goto out; @@ -1018,8 +1018,8 @@ RemoteGDB::trap(int type) case KGDB_STEP: if (p - data < datalen) { val = hex2i(&p); - context->regs.pc = val; - context->regs.npc = val + sizeof(MachInst); + context->setPC(val); + context->setNextPC(val + sizeof(MachInst)); } setSingleStep(); goto out; -- cgit v1.2.3 From cd62fed1a7c535befaa00c8775de78f9f29b1274 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Mar 2006 09:34:24 -0500 Subject: The a.out and ecoff object file formats will only be supported on Alpha for now. arch/SConscript: aout_machdep.h and ecoff_machdep.h are no longer bridging headers, since support of these formats is limitted to alpha. base/loader/exec_aout.h: Include the alpha specific version of aout_machdep.h, since only the alpha version of aout will be supported for now. base/loader/exec_ecoff.h: Include the alpha specific version of ecoff_machdep.h, since only the alpha version of ecoff will be supported for now. --HG-- extra : convert_revision : 15328aae54538c26d2c10d7476501e0daa3d22d0 --- base/loader/exec_aout.h | 3 ++- base/loader/exec_ecoff.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'base') diff --git a/base/loader/exec_aout.h b/base/loader/exec_aout.h index 3863a92fb..eed44baee 100644 --- a/base/loader/exec_aout.h +++ b/base/loader/exec_aout.h @@ -55,6 +55,7 @@ (N_GETMAGIC(ex) != NMAGIC && N_GETMAGIC(ex) != OMAGIC && \ N_GETMAGIC(ex) != ZMAGIC) -#include "arch/aout_machdep.h" +//Only alpha will be able to load aout for now +#include "arch/alpha/aout_machdep.h" #endif /* !_SYS_EXEC_AOUT_H_ */ diff --git a/base/loader/exec_ecoff.h b/base/loader/exec_ecoff.h index 79cd22a6e..555589806 100644 --- a/base/loader/exec_ecoff.h +++ b/base/loader/exec_ecoff.h @@ -37,7 +37,8 @@ #ifndef _SYS_EXEC_ECOFF_H_ #define _SYS_EXEC_ECOFF_H_ -#include "arch/ecoff_machdep.h" +//Only alpha will be able to load ecoff files for now +#include "arch/alpha/ecoff_machdep.h" struct ecoff_filehdr { coff_ushort f_magic; /* magic number */ -- cgit v1.2.3 From ce3a6343b6c54e95d63403d46c9ddea384e49476 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 9 Mar 2006 15:42:09 -0500 Subject: no more common syscall emulation, now common for everyone check abi-tag note section of elf binary for OS add pseudo functions (moved from alpha and made to be generic) move setsyscallreturn into isa traits arch/alpha/SConscript: no more common syscall emulation, now common for everyone arch/alpha/isa_traits.hh: move setsyscallreturn into isa description arch/alpha/linux/process.cc: arch/alpha/tru64/process.cc: use generic functions rather than alpha specific ones arch/sparc/isa_traits.hh: have consts for generic pseudo syscalls arch/sparc/linux/process.cc: use generic functions base/loader/elf_object.cc: check abi-tag note section of elf binary for OS cpu/exec_context.hh: move syssyscallreturn into isa traits sim/process.cc: find call num with a more generic sim/syscall_emul.cc: sim/syscall_emul.hh: add pseudo functions (moved from alpha and made to be generic) --HG-- extra : convert_revision : 5a31024ecde7e39b830365ddd84593ea501a34d2 --- base/loader/elf_object.cc | 53 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 44 insertions(+), 9 deletions(-) (limited to 'base') diff --git a/base/loader/elf_object.cc b/base/loader/elf_object.cc index fd69c9e56..791c6f6de 100644 --- a/base/loader/elf_object.cc +++ b/base/loader/elf_object.cc @@ -75,15 +75,6 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data) return NULL; } else { -// if (ehdr.e_ident[EI_CLASS] == ELFCLASS32) -// panic("32 bit ELF Binary, Not Supported"); - /* @todo this emachine value isn't offical yet. - * so we probably shouldn't check it. */ -// if (ehdr.e_machine != EM_ALPHA) -// panic("Non Alpha Binary, Not Supported"); - - elf_end(elf); - //Detect the architecture //Versioning issues in libelf need to be resolved to get the correct //SPARC constants. @@ -109,17 +100,61 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data) //Detect the operating system switch (ehdr.e_ident[EI_OSABI]) { + case ELFOSABI_LINUX: opSys = ObjectFile::Linux; break; case ELFOSABI_SOLARIS: opSys = ObjectFile::Solaris; + break; case ELFOSABI_TRU64: opSys = ObjectFile::Tru64; + break; default: opSys = ObjectFile::UnknownOpSys; } + //take a look at the .note.ABI section + //It can let us know what's what. + if (opSys == ObjectFile::UnknownOpSys) + { + Elf_Scn *section; + GElf_Shdr shdr; + Elf_Data *data; + uint32_t osAbi;; + int secIdx = 1; + + // Get the first section + section = elf_getscn(elf, secIdx); + + // While there are no more sections + while (section != NULL) { + gelf_getshdr(section, &shdr); + if (shdr.sh_type == SHT_NOTE && !strcmp(".note.ABI-tag", + elf_strptr(elf, ehdr.e_shstrndx, shdr.sh_name))) { + // we have found a ABI note section + // Check the 5th 32bit word for OS 0 == linux, 1 == hurd, + // 2 == solaris, 3 == freebsd + data = elf_rawdata(section, NULL); + assert(data->d_buf); + if(ehdr.e_ident[EI_DATA] == ELFDATA2LSB) + osAbi = htole(((uint32_t*)data->d_buf)[4]); + else + osAbi = htobe(((uint32_t*)data->d_buf)[4]); + + switch(osAbi) { + case 0: + opSys = ObjectFile::Linux; + break; + case 2: + opSys = ObjectFile::Solaris; + break; + } + } // if section found + section = elf_getscn(elf, ++secIdx); + } // while sections + } + elf_end(elf); return new ElfObject(fname, fd, len, data, arch, opSys); } } -- cgit v1.2.3