From 126c0360e2efd9588f38128bad94c7fa82c79f25 Mon Sep 17 00:00:00 2001 From: Alec Roelke Date: Wed, 30 Nov 2016 17:10:28 -0500 Subject: riscv: [Patch 5/5] Added missing support for timing CPU models Last of five patches adding RISC-V to GEM5. This patch adds support for timing, minor, and detailed CPU models that was missing in the last four, which basically consists of handling timing-mode memory accesses and telling the minor and detailed models what a no-op instruction should be (addi zero, zero, 0). Patches 1-4 introduced RISC-V and implemented the base instruction set, RV64I, and added the multiply, floating point, and atomic memory extensions, RV64MAFD. [Fixed compatibility with edit from patch 1.] [Fixed compatibility with hg copy edit from patch 1.] [Fixed some style errors in locked_mem.hh.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power --- build_opts/RISCV | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'build_opts') diff --git a/build_opts/RISCV b/build_opts/RISCV index 3b5053a79..38abd9216 100644 --- a/build_opts/RISCV +++ b/build_opts/RISCV @@ -1,3 +1,3 @@ TARGET_ISA = 'riscv' -CPU_MODELS = 'AtomicSimpleCPU' +CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,MinorCPU,O3CPU' PROTOCOL = 'MI_example' -- cgit v1.2.3