From 4459b305251109ff147d72142452e25c74542ebd Mon Sep 17 00:00:00 2001 From: Akash Bagdia Date: Thu, 27 Jun 2013 05:49:49 -0400 Subject: config: Add a CPU clock command-line option This patch adds a 'cpu_clock' command-line option and uses the value to assign clocks to components running at the CPU speed (L1 and L2 including the L2-bus). The configuration scripts are updated accordingly. The 'clock' option is left unchanged in this patch as it is still used by a number of components. In follow-on patches the latter will be disambiguated further. --- configs/common/CacheConfig.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'configs/common/CacheConfig.py') diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 5dd564f0c..288a633ce 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -64,12 +64,12 @@ def config_cache(options, system): # are not connected using addTwoLevelCacheHierarchy. Use the # same clock as the CPUs, and set the L1-to-L2 bus width to 32 # bytes (256 bits). - system.l2 = l2_cache_class(clock=options.clock, + system.l2 = l2_cache_class(clock=options.cpu_clock, size=options.l2_size, assoc=options.l2_assoc, block_size=options.cacheline_size) - system.tol2bus = CoherentBus(clock = options.clock, width = 32) + system.tol2bus = CoherentBus(clock = options.cpu_clock, width = 32) system.l2.cpu_side = system.tol2bus.master system.l2.mem_side = system.membus.slave -- cgit v1.2.3