From c3268f882029c7501867540ccf04db054fdff084 Mon Sep 17 00:00:00 2001 From: Curtis Dunham Date: Wed, 8 Apr 2015 15:56:06 -0500 Subject: config: Support full-system with SST's memory system This patch adds an example configuration in ext/sst/tests/ that allows an SST/gem5 instance to simulate a 4-core AArch64 system with SST's memHierarchy components providing all the caches and memories. --- configs/common/CacheConfig.py | 49 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) (limited to 'configs/common/CacheConfig.py') diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 66fe491e1..899090af5 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012-2013 ARM Limited +# Copyright (c) 2012-2013, 2015 ARM Limited # All rights reserved # # The license below extends only to copyright in the software and shall @@ -46,6 +46,13 @@ from m5.objects import * from Caches import * def config_cache(options, system): + if options.external_memory_system and (options.caches or options.l2cache): + print "External caches and internal caches are exclusive options.\n" + sys.exit(1) + + if options.external_memory_system: + ExternalCache = ExternalCacheFactory(options.external_memory_system) + if options.cpu_type == "arm_detailed": try: from O3_ARM_v7a import * @@ -114,10 +121,50 @@ def config_cache(options, system): system.cpu[i].dcache = dcache_real system.cpu[i].dcache_mon = dcache_mon + elif options.external_memory_system: + # These port names are presented to whatever 'external' system + # gem5 is connecting to. Its configuration will likely depend + # on these names. For simplicity, we would advise configuring + # it to use this naming scheme; if this isn't possible, change + # the names below. + if buildEnv['TARGET_ISA'] in ['x86', 'arm']: + system.cpu[i].addPrivateSplitL1Caches( + ExternalCache("cpu%d.icache" % i), + ExternalCache("cpu%d.dcache" % i), + ExternalCache("cpu%d.itb_walker_cache" % i), + ExternalCache("cpu%d.dtb_walker_cache" % i)) + else: + system.cpu[i].addPrivateSplitL1Caches( + ExternalCache("cpu%d.icache" % i), + ExternalCache("cpu%d.dcache" % i)) + system.cpu[i].createInterruptController() if options.l2cache: system.cpu[i].connectAllPorts(system.tol2bus, system.membus) + elif options.external_memory_system: + system.cpu[i].connectUncachedPorts(system.membus) else: system.cpu[i].connectAllPorts(system.membus) return system + +# ExternalSlave provides a "port", but when that port connects to a cache, +# the connecting CPU SimObject wants to refer to its "cpu_side". +# The 'ExternalCache' class provides this adaptation by rewriting the name, +# eliminating distracting changes elsewhere in the config code. +class ExternalCache(ExternalSlave): + def __getattr__(cls, attr): + if (attr == "cpu_side"): + attr = "port" + return super(ExternalSlave, cls).__getattr__(attr) + + def __setattr__(cls, attr, value): + if (attr == "cpu_side"): + attr = "port" + return super(ExternalSlave, cls).__setattr__(attr, value) + +def ExternalCacheFactory(port_type): + def make(name): + return ExternalCache(port_data=name, port_type=port_type, + addr_ranges=[AllMemory]) + return make -- cgit v1.2.3