From ce2722cdd97a31f85d36f6c32637b230e3c25c73 Mon Sep 17 00:00:00 2001 From: Sophiane Senni Date: Wed, 30 Nov 2016 17:10:27 -0500 Subject: mem: Split the hit_latency into tag_latency and data_latency If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Signed-off-by: Jason Lowe-Power --- configs/common/O3_ARM_v7a.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'configs/common/O3_ARM_v7a.py') diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py index 3def4a3f2..f5c2c711a 100644 --- a/configs/common/O3_ARM_v7a.py +++ b/configs/common/O3_ARM_v7a.py @@ -147,7 +147,8 @@ class O3_ARM_v7a_3(DerivO3CPU): # Instruction Cache class O3_ARM_v7a_ICache(Cache): - hit_latency = 1 + tag_latency = 1 + data_latency = 1 response_latency = 1 mshrs = 2 tgts_per_mshr = 8 @@ -159,7 +160,8 @@ class O3_ARM_v7a_ICache(Cache): # Data Cache class O3_ARM_v7a_DCache(Cache): - hit_latency = 2 + tag_latency = 2 + data_latency = 2 response_latency = 2 mshrs = 6 tgts_per_mshr = 8 @@ -172,7 +174,8 @@ class O3_ARM_v7a_DCache(Cache): # TLB Cache # Use a cache as a L2 TLB class O3_ARM_v7aWalkCache(Cache): - hit_latency = 4 + tag_latency = 4 + data_latency = 4 response_latency = 4 mshrs = 6 tgts_per_mshr = 8 @@ -185,7 +188,8 @@ class O3_ARM_v7aWalkCache(Cache): # L2 Cache class O3_ARM_v7aL2(Cache): - hit_latency = 12 + tag_latency = 12 + data_latency = 12 response_latency = 12 mshrs = 16 tgts_per_mshr = 8 -- cgit v1.2.3