From f763864786d7b95d46fba6f37e1e9ed601b60733 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 31 Oct 2006 14:58:09 -0500 Subject: Fix up configs. configs/common/Simulation.py: Remove mem parameter. configs/example/se.py: Remove debug output that got included in my other push. --HG-- extra : convert_revision : 643c34147f6c6cbb98b8e6d6e8206b9859593ab0 --- configs/common/Simulation.py | 2 -- 1 file changed, 2 deletions(-) (limited to 'configs/common/Simulation.py') diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 5e9c1d339..a05e36bd1 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -67,8 +67,6 @@ def run(options, root, testsys): switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) - switch_cpus[i].mem = testsys.physmem - switch_cpus1[i].mem = testsys.physmem switch_cpus[i].connectMemPorts(testsys.membus) root.switch_cpus = switch_cpus root.switch_cpus1 = switch_cpus1 -- cgit v1.2.3 From 9ef8bf74c7ab3d34889e804cb4b1e365da090d0b Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Wed, 1 Nov 2006 11:40:49 -0500 Subject: change name of 2nd switch_cpu so that ckpt recovery with multiple cpus doens't get confused. --HG-- extra : convert_revision : 16c710c4196c520d03c1993a26f38cf1f04ab637 --- configs/common/Simulation.py | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'configs/common/Simulation.py') diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index a05e36bd1..a2b1d84d2 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -53,25 +53,27 @@ def run(options, root, testsys): if options.standard_switch: switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) for i in xrange(np)] - switch_cpus1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) + switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) for i in xrange(np)] + for i in xrange(np): switch_cpus[i].system = testsys - switch_cpus1[i].system = testsys + switch_cpus_1[i].system = testsys if not m5.build_env['FULL_SYSTEM']: switch_cpus[i].workload = testsys.cpu[i].workload - switch_cpus1[i].workload = testsys.cpu[i].workload + switch_cpus_1[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[0].clock - switch_cpus1[i].clock = testsys.cpu[0].clock + switch_cpus_1[i].clock = testsys.cpu[0].clock if options.caches: switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) switch_cpus[i].connectMemPorts(testsys.membus) + root.switch_cpus = switch_cpus - root.switch_cpus1 = switch_cpus1 + root.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] - switch_cpu_list1 = [(switch_cpus[i], switch_cpus1[i]) for i in xrange(np)] + switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] m5.instantiate(root) -- cgit v1.2.3 From 7665be4f7066dcc65cacc010ca740a01d57e08d5 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Wed, 1 Nov 2006 11:49:39 -0500 Subject: make it so that you can do a standard switch without the caches option. this will have only the o3 cpu have a cache, rather than timing (warmup) + o3 have cache. --HG-- extra : convert_revision : d733de7ebb362bbd7376a0235ee7f117df2d6d37 --- configs/common/Simulation.py | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'configs/common/Simulation.py') diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index a2b1d84d2..a10d588fa 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -64,9 +64,16 @@ def run(options, root, testsys): switch_cpus_1[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[0].clock switch_cpus_1[i].clock = testsys.cpu[0].clock + + ## add caches to the warmup timing CPU (which will be + ## xferred to O3 when you switch again) if options.caches: switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) + else: # O3 CPU must have a cache to work. + switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), + L1Cache(size = '64kB')) + switch_cpus_1[i].connectMemPorts(testsys.membus) switch_cpus[i].connectMemPorts(testsys.membus) -- cgit v1.2.3 From 74ff45d353fadb8dd70f4fd9135ab66ce71e6718 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Wed, 1 Nov 2006 19:25:09 -0500 Subject: factor some more commone code and enable going from checkpoint into arbitrary CPU with or without caches. configs/common/Simulation.py: enable going from checkpoint into arbitrary CPU with or without caches. --HG-- extra : convert_revision : 02e7ff8982fdb3a08bc609f89bd58df5b3a581b2 --- configs/common/Simulation.py | 58 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 50 insertions(+), 8 deletions(-) (limited to 'configs/common/Simulation.py') diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index a10d588fa..d88373d54 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -32,7 +32,31 @@ from m5.objects import * m5.AddToPath('../common') from Caches import L1Cache -def run(options, root, testsys): +def setCPUClass(options): + + atomic = False + if options.timing: + TmpClass = TimingSimpleCPU + elif options.detailed: + TmpClass = DerivO3CPU + else: + TmpClass = AtomicSimpleCPU + atomic = True + + CPUClass = None + test_mem_mode = 'atomic' + + if not atomic: + if options.checkpoint_restore: + CPUClass = TmpClass + TmpClass = AtomicSimpleCPU + else: + test_mem_mode = 'timing' + + return (TmpClass, test_mem_mode, CPUClass) + + +def run(options, root, testsys, cpu_class): if options.maxtick: maxtick = options.maxtick elif options.maxtime: @@ -49,6 +73,24 @@ def run(options, root, testsys): np = options.num_cpus max_checkpoints = options.max_checkpoints + switch_cpus = None + + if cpu_class: + switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i)) + for i in xrange(np)] + + for i in xrange(np): + switch_cpus[i].system = testsys + if not m5.build_env['FULL_SYSTEM']: + switch_cpus[i].workload = testsys.cpu[i].workload + switch_cpus[i].clock = testsys.cpu[0].clock + if options.caches: + switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), + L1Cache(size = '64kB')) + switch_cpus[i].connectMemPorts(testsys.membus) + + root.switch_cpus = switch_cpus + switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] if options.standard_switch: switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) @@ -65,17 +107,16 @@ def run(options, root, testsys): switch_cpus[i].clock = testsys.cpu[0].clock switch_cpus_1[i].clock = testsys.cpu[0].clock - ## add caches to the warmup timing CPU (which will be - ## xferred to O3 when you switch again) if options.caches: switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) - else: # O3 CPU must have a cache to work. + switch_cpus[i].connectMemPorts(testsys.membus) + else: + # O3 CPU must have a cache to work. switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) switch_cpus_1[i].connectMemPorts(testsys.membus) - switch_cpus[i].connectMemPorts(testsys.membus) root.switch_cpus = switch_cpus root.switch_cpus_1 = switch_cpus_1 @@ -110,7 +151,7 @@ def run(options, root, testsys): m5.restoreCheckpoint(root, "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]])) - if options.standard_switch: + if options.standard_switch or cpu_class: exit_event = m5.simulate(10000) ## when you change to Timing (or Atomic), you halt the system given @@ -123,8 +164,9 @@ def run(options, root, testsys): m5.switchCpus(switch_cpu_list) m5.resume(testsys) - exit_event = m5.simulate(options.warmup) - m5.switchCpus(switch_cpu_list1) + if options.standard_switch: + exit_event = m5.simulate(options.warmup) + m5.switchCpus(switch_cpu_list1) num_checkpoints = 0 exit_cause = '' -- cgit v1.2.3 From 0a0d9cd3ab598f80f80834fa62e5aa397db3ef6c Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Wed, 8 Nov 2006 14:01:23 -0500 Subject: change to os.path.join like nate wanted. --HG-- extra : convert_revision : 6e8a0153adf04f0cc07904434e4cb6a83fe900eb --- configs/common/Simulation.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'configs/common/Simulation.py') diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index d88373d54..afa147537 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -27,6 +27,7 @@ # Authors: Lisa Hsu from os import getcwd +from os.path import join as joinpath import m5 from m5.objects import * m5.AddToPath('../common') @@ -149,7 +150,7 @@ def run(options, root, testsys, cpu_class): m5.panic('Checkpoint %d not found' % cpt_num) m5.restoreCheckpoint(root, - "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]])) + joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1])) if options.standard_switch or cpu_class: exit_event = m5.simulate(10000) @@ -184,7 +185,7 @@ def run(options, root, testsys, cpu_class): exit_event = m5.simulate(when - m5.curTick()) if exit_event.getCause() == "simulate() limit reached": - m5.checkpoint(root, "/".join([cptdir,"cpt.%d"])) + m5.checkpoint(root, joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 sim_ticks = when @@ -200,14 +201,14 @@ def run(options, root, testsys, cpu_class): while exit_event.getCause() == "checkpoint": exit_event = m5.simulate(sim_ticks - m5.curTick()) if exit_event.getCause() == "simulate() limit reached": - m5.checkpoint(root, "/".join([cptdir,"cpt.%d"])) + m5.checkpoint(root, joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 else: #no checkpoints being taken via this script exit_event = m5.simulate(maxtick) while exit_event.getCause() == "checkpoint": - m5.checkpoint(root, "/".join([cptdir,"cpt.%d"])) + m5.checkpoint(root, joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 if num_checkpoints == max_checkpoints: exit_cause = "maximum %d checkpoints dropped" % max_checkpoints -- cgit v1.2.3 From 64c0d82dec8ae042d41b6dbaa17a40095bb09091 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Wed, 8 Nov 2006 15:05:23 -0500 Subject: simplify maxtick parsing in both the python and the c++. configs/common/Simulation.py: simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick. src/python/m5/__init__.py: make a new m5 param called MaxTick. src/sim/host.hh: fix the M5 def. of MaxTick src/sim/main.cc: Simplify the MaxTick/num_cycles parsing within main.cc --HG-- extra : convert_revision : f800addfbc1323591c2e05b892276b439b671668 --- configs/common/Simulation.py | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'configs/common/Simulation.py') diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index afa147537..a67159a50 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -65,7 +65,7 @@ def run(options, root, testsys, cpu_class): print "simulating for: ", simtime maxtick = simtime else: - maxtick = -1 + maxtick = m5.MaxTick if options.checkpoint_dir: cptdir = options.checkpoint_dir @@ -191,7 +191,7 @@ def run(options, root, testsys, cpu_class): sim_ticks = when exit_cause = "maximum %d checkpoints dropped" % max_checkpoints while num_checkpoints < max_checkpoints: - if (sim_ticks + period) > maxtick and maxtick != -1: + if (sim_ticks + period) > maxtick: exit_event = m5.simulate(maxtick - sim_ticks) exit_cause = exit_event.getCause() break @@ -214,11 +214,7 @@ def run(options, root, testsys, cpu_class): exit_cause = "maximum %d checkpoints dropped" % max_checkpoints break - if maxtick == -1: - exit_event = m5.simulate(maxtick) - else: - exit_event = m5.simulate(maxtick - m5.curTick()) - + exit_event = m5.simulate(maxtick - m5.curTick()) exit_cause = exit_event.getCause() if exit_cause == '': -- cgit v1.2.3