From 1f6d5f8f849f50a3646f586b1274708537124ef3 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Sat, 20 Sep 2014 17:18:32 -0400 Subject: mem: Rename Bus to XBar to better reflect its behaviour This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. --HG-- rename : src/mem/Bus.py => src/mem/XBar.py rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh rename : src/mem/bus.cc => src/mem/xbar.cc rename : src/mem/bus.hh => src/mem/xbar.hh --- configs/common/CacheConfig.py | 4 ++-- configs/common/FSConfig.py | 14 +++++++------- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'configs/common') diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index b467b1656..c7a724b34 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -71,8 +71,8 @@ def config_cache(options, system): size=options.l2_size, assoc=options.l2_assoc) - system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain, - width = 32) + system.tol2bus = CoherentXBar(clk_domain = system.cpu_clk_domain, + width = 32) system.l2.cpu_side = system.tol2bus.master system.l2.mem_side = system.membus.slave diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index cc921229e..e93bd68f2 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -50,7 +50,7 @@ class CowIdeDisk(IdeDisk): def childImage(self, ci): self.image.child.image_file = ci -class MemBus(CoherentBus): +class MemBus(CoherentXBar): badaddr_responder = BadAddr() default = Self.badaddr_responder.pio @@ -71,7 +71,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False): self.tsunami = BaseTsunami() # Create the io bus to connect all device ports - self.iobus = NoncoherentBus() + self.iobus = NoncoherentXBar() self.tsunami.attachIO(self.iobus) self.tsunami.ide.pio = self.iobus.master @@ -134,7 +134,7 @@ def makeSparcSystem(mem_mode, mdesc = None): # generic system mdesc = SysConfig() self.readfile = mdesc.script() - self.iobus = NoncoherentBus() + self.iobus = NoncoherentXBar() self.membus = MemBus() self.bridge = Bridge(delay='50ns') self.t1000 = T1000() @@ -196,7 +196,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, mdesc = SysConfig() self.readfile = mdesc.script() - self.iobus = NoncoherentBus() + self.iobus = NoncoherentXBar() self.membus = MemBus() self.membus.badaddr_responder.warn_access = "warn" self.bridge = Bridge(delay='50ns') @@ -299,7 +299,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None): # generic system mdesc = SysConfig() self.readfile = mdesc.script() - self.iobus = NoncoherentBus() + self.iobus = NoncoherentXBar() self.membus = MemBus() self.bridge = Bridge(delay='50ns') self.mem_ranges = [AddrRange('1GB')] @@ -344,7 +344,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs): x86_sys.membus = MemBus() # North Bridge - x86_sys.iobus = NoncoherentBus() + x86_sys.iobus = NoncoherentXBar() x86_sys.bridge = Bridge(delay='50ns') x86_sys.bridge.master = x86_sys.iobus.slave x86_sys.bridge.slave = x86_sys.membus.master @@ -379,7 +379,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs): def connectX86RubySystem(x86_sys): # North Bridge - x86_sys.iobus = NoncoherentBus() + x86_sys.iobus = NoncoherentXBar() # add the ide to the list of dma devices that later need to attach to # dma controllers -- cgit v1.2.3