From 634d2e9d83054d2ddae4333d4e28e9a04cfbfd84 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 10 May 2007 18:24:48 -0400 Subject: remove hit_latency and make latency do the right thing set the latency parameter in terms of a latency add caches to tsunami-simple configs configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs --HG-- extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1 --- configs/common/Caches.py | 6 +++--- configs/common/FSConfig.py | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'configs/common') diff --git a/configs/common/Caches.py b/configs/common/Caches.py index 4692ef537..4bff2c8a4 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -32,7 +32,7 @@ from m5.objects import * class L1Cache(BaseCache): assoc = 2 block_size = 64 - latency = 1 + latency = '1ns' mshrs = 10 tgts_per_mshr = 5 protocol = CoherenceProtocol(protocol='moesi') @@ -40,7 +40,7 @@ class L1Cache(BaseCache): class L2Cache(BaseCache): assoc = 8 block_size = 64 - latency = 10 + latency = '10ns' mshrs = 20 tgts_per_mshr = 12 diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 289a7a5f4..593baf169 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -61,7 +61,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): self.readfile = mdesc.script() self.iobus = Bus(bus_id=0) self.membus = Bus(bus_id=1) - self.bridge = Bridge(fix_partial_write_b=True) + self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns') self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) self.bridge.side_a = self.iobus.port self.bridge.side_b = self.membus.port @@ -94,7 +94,7 @@ def makeSparcSystem(mem_mode, mdesc = None): self.readfile = mdesc.script() self.iobus = Bus(bus_id=0) self.membus = Bus(bus_id=1) - self.bridge = Bridge() + self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns') self.t1000 = T1000() self.t1000.attachOnChipIO(self.membus) self.t1000.attachIO(self.iobus) -- cgit v1.2.3