From 7433d77fcf74ddcd6052a60e0251a1d5d1a46e44 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Fri, 6 Nov 2015 03:26:43 -0500 Subject: mem: Add an option to perform clean writebacks from caches This patch adds the necessary commands and cache functionality to allow clean writebacks. This functionality is crucial, especially when having exclusive (victim) caches. For example, if read-only L1 instruction caches are not sending clean writebacks, there will never be any spills from the L1 to the L2. At the moment the cache model defaults to not sending clean writebacks, and this should possibly be re-evaluated. The implementation of clean writebacks relies on a new packet command WritebackClean, which acts much like a Writeback (renamed WritebackDirty), and also much like a CleanEvict. On eviction of a clean block the cache either sends a clean evict, or a clean writeback, and if any copies are still cached upstream the clean evict/writeback is dropped. Similarly, if a clean evict/writeback reaches a cache where there are outstanding MSHRs for the block, the packet is dropped. In the typical case though, the clean writeback allocates a block in the downstream cache, and marks it writable if the evicted block was writable. The patch changes the O3_ARM_v7a L1 cache configuration and the default L1 caches in config/common/Caches.py --- configs/common/Caches.py | 4 ++++ configs/common/O3_ARM_v7a.py | 6 ++++++ 2 files changed, 10 insertions(+) (limited to 'configs/common') diff --git a/configs/common/Caches.py b/configs/common/Caches.py index 0a3c56297..c65910e23 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -55,6 +55,8 @@ class L1Cache(Cache): class L1_ICache(L1Cache): is_read_only = True + # Writeback clean lines as well + writeback_clean = True class L1_DCache(L1Cache): pass @@ -89,3 +91,5 @@ class PageTableWalkerCache(Cache): is_read_only = False else: is_read_only = True + # Writeback clean lines as well + writeback_clean = True diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py index 02beb11d1..103158290 100644 --- a/configs/common/O3_ARM_v7a.py +++ b/configs/common/O3_ARM_v7a.py @@ -151,6 +151,8 @@ class O3_ARM_v7a_ICache(Cache): assoc = 2 forward_snoops = False is_read_only = True + # Writeback clean lines as well + writeback_clean = True # Data Cache class O3_ARM_v7a_DCache(Cache): @@ -161,6 +163,8 @@ class O3_ARM_v7a_DCache(Cache): size = '32kB' assoc = 2 write_buffers = 16 + # Consider the L2 a victim cache also for clean lines + writeback_clean = True # TLB Cache # Use a cache as a L2 TLB @@ -174,6 +178,8 @@ class O3_ARM_v7aWalkCache(Cache): write_buffers = 16 forward_snoops = False is_read_only = True + # Writeback clean lines as well + writeback_clean = True # L2 Cache class O3_ARM_v7aL2(Cache): -- cgit v1.2.3