From 8a53da22c2f07aed924a45ab296f7468d842d7f6 Mon Sep 17 00:00:00 2001 From: Anthony Gutierrez Date: Fri, 15 Nov 2013 13:21:15 -0500 Subject: cpu: allow the fetch buffer to be smaller than a cache line the current implementation of the fetch buffer in the o3 cpu is only allowed to be the size of a cache line. some architectures, e.g., ARM, have fetch buffers smaller than a cache line, see slide 22 at: http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf this patch allows the fetch buffer to be set to values smaller than a cache line. --- configs/common/O3_ARM_v7a.py | 1 + 1 file changed, 1 insertion(+) (limited to 'configs/common') diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py index 10d466419..aedafaf4d 100644 --- a/configs/common/O3_ARM_v7a.py +++ b/configs/common/O3_ARM_v7a.py @@ -119,6 +119,7 @@ class O3_ARM_v7a_3(DerivO3CPU): commitToRenameDelay = 1 commitToIEWDelay = 1 fetchWidth = 3 + fetchBufferSize = 16 fetchToDecodeDelay = 3 decodeWidth = 3 decodeToRenameDelay = 2 -- cgit v1.2.3