From c20105c2ff2b8300fa18a5c3f1afb806d6ae9458 Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson>
Date: Thu, 18 Jul 2013 08:31:19 -0400
Subject: config: Update script to set cache line size on system

This patch changes the config scripts such that they do not set the
cache line size per cache instance, but rather for the system as a
whole.
---
 configs/common/CacheConfig.py | 12 ++++++------
 configs/common/Caches.py      |  4 ----
 configs/common/O3_ARM_v7a.py  |  4 ----
 3 files changed, 6 insertions(+), 14 deletions(-)

(limited to 'configs/common')

diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 4b4ce7553..b467b1656 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -59,6 +59,9 @@ def config_cache(options, system):
         dcache_class, icache_class, l2_cache_class = \
             L1Cache, L1Cache, L2Cache
 
+    # Set the cache line size of the system
+    system.cache_line_size = options.cacheline_size
+
     if options.l2cache:
         # Provide a clock for the L2 and the L1-to-L2 bus here as they
         # are not connected using addTwoLevelCacheHierarchy. Use the
@@ -66,8 +69,7 @@ def config_cache(options, system):
         # bytes (256 bits).
         system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
                                    size=options.l2_size,
-                                   assoc=options.l2_assoc,
-                                   block_size=options.cacheline_size)
+                                   assoc=options.l2_assoc)
 
         system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
                                      width = 32)
@@ -77,11 +79,9 @@ def config_cache(options, system):
     for i in xrange(options.num_cpus):
         if options.caches:
             icache = icache_class(size=options.l1i_size,
-                                  assoc=options.l1i_assoc,
-                                  block_size=options.cacheline_size)
+                                  assoc=options.l1i_assoc)
             dcache = dcache_class(size=options.l1d_size,
-                                  assoc=options.l1d_assoc,
-                                  block_size=options.cacheline_size)
+                                  assoc=options.l1d_assoc)
 
             # When connecting the caches, the clock is also inherited
             # from the CPU in question
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 6f1aff443..9f7ac7a85 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -50,14 +50,12 @@ class L1Cache(BaseCache):
     assoc = 2
     hit_latency = 2
     response_latency = 2
-    block_size = 64
     mshrs = 4
     tgts_per_mshr = 20
     is_top_level = True
 
 class L2Cache(BaseCache):
     assoc = 8
-    block_size = 64
     hit_latency = 20
     response_latency = 20
     mshrs = 20
@@ -66,7 +64,6 @@ class L2Cache(BaseCache):
 
 class IOCache(BaseCache):
     assoc = 8
-    block_size = 64
     hit_latency = 50
     response_latency = 50
     mshrs = 20
@@ -77,7 +74,6 @@ class IOCache(BaseCache):
 
 class PageTableWalkerCache(BaseCache):
     assoc = 2
-    block_size = 64
     hit_latency = 2
     response_latency = 2
     mshrs = 10
diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py
index f5cd3bbc8..10d466419 100644
--- a/configs/common/O3_ARM_v7a.py
+++ b/configs/common/O3_ARM_v7a.py
@@ -149,7 +149,6 @@ class O3_ARM_v7a_3(DerivO3CPU):
 class O3_ARM_v7a_ICache(BaseCache):
     hit_latency = 1
     response_latency = 1
-    block_size = 64
     mshrs = 2
     tgts_per_mshr = 8
     size = '32kB'
@@ -160,7 +159,6 @@ class O3_ARM_v7a_ICache(BaseCache):
 class O3_ARM_v7a_DCache(BaseCache):
     hit_latency = 2
     response_latency = 2
-    block_size = 64
     mshrs = 6
     tgts_per_mshr = 8
     size = '32kB'
@@ -173,7 +171,6 @@ class O3_ARM_v7a_DCache(BaseCache):
 class O3_ARM_v7aWalkCache(BaseCache):
     hit_latency = 4
     response_latency = 4
-    block_size = 64
     mshrs = 6
     tgts_per_mshr = 8
     size = '1kB'
@@ -186,7 +183,6 @@ class O3_ARM_v7aWalkCache(BaseCache):
 class O3_ARM_v7aL2(BaseCache):
     hit_latency = 12
     response_latency = 12
-    block_size = 64
     mshrs = 16
     tgts_per_mshr = 8
     size = '1MB'
-- 
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