From f85286b3debf4a4a94d3b959e5bb880be81bd692 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Tue, 17 Jan 2012 12:55:08 -0600 Subject: MEM: Add port proxies instead of non-structural ports Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy. The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy --HG-- rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh --- configs/common/FSConfig.py | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'configs/common') diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index f54d63852..3c506c215 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -1,4 +1,4 @@ -# Copyright (c) 2010 ARM Limited +# Copyright (c) 2010-2012 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -91,6 +91,8 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): self.console = binary('console') self.boot_osflags = 'root=/dev/hda1 console=ttyS0' + self.system_port = self.membus.port + return self def makeLinuxAlphaRubySystem(mem_mode, mdesc = None): @@ -183,6 +185,8 @@ def makeSparcSystem(mem_mode, mdesc = None): self.hypervisor_desc_bin = binary('1up-hv.bin') self.partition_desc_bin = binary('1up-md.bin') + self.system_port = self.membus.port + return self def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): @@ -263,6 +267,8 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): self.terminal = Terminal() self.vncserver = VncServer() + self.system_port = self.membus.port + return self @@ -301,6 +307,8 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None): self.console = binary('mips/console') self.boot_osflags = 'root=/dev/hda1 console=ttyS0' + self.system_port = self.membus.port + return self def x86IOAddress(port): @@ -320,6 +328,8 @@ def connectX86ClassicSystem(x86_sys): # connect the io bus x86_sys.pc.attachIO(x86_sys.iobus) + x86_sys.system_port = x86_sys.membus.port + def connectX86RubySystem(x86_sys): # North Bridge x86_sys.piobus = Bus(bus_id=0) -- cgit v1.2.3 From 2208ea049f60618e432c69c065926bcbc810581a Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Tue, 17 Jan 2012 12:55:09 -0600 Subject: MEM: Make the bus bridge unidirectional and fixed address range This patch makes the bus bridge uni-directional and specialises the bus ports to be a master port and a slave port. This greatly simplifies the assumptions on both sides as either port only has to deal with requests or responses. The following patches introduce the notion of master and slave ports, and would not be possible without this split of responsibilities. In making the bridge unidirectional, the address range mechanism of the bridge is also changed. For the cases where communication is taking place both ways, an additional bridge is needed. This causes issues with the existing mechanism, as the busses cannot determine when to stop iterating the address updates from the two bridges. To avoid this issue, and also greatly simplify the specification, the bridge now has a fixed set of address ranges, specified at creation time. --- configs/common/FSConfig.py | 79 +++++++++++++++++++++++++++++++++++++++------- 1 file changed, 67 insertions(+), 12 deletions(-) (limited to 'configs/common') diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 3c506c215..8407db869 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -56,6 +56,7 @@ class MemBus(Bus): def makeLinuxAlphaSystem(mem_mode, mdesc = None): + IO_address_space_base = 0x80000000000 class BaseTsunami(Tsunami): ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) ide = IdeController(disks=[Parent.disk0, Parent.disk2], @@ -68,10 +69,13 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): self.readfile = mdesc.script() self.iobus = Bus(bus_id=0) self.membus = MemBus(bus_id=1) - self.bridge = Bridge(delay='50ns', nack_delay='4ns') + # By default the bridge responds to all addresses above the I/O + # base address (including the PCI config space) + self.bridge = Bridge(delay='50ns', nack_delay='4ns', + ranges = [AddrRange(IO_address_space_base, Addr.max)]) self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) - self.bridge.side_a = self.iobus.port - self.bridge.side_b = self.membus.port + self.bridge.master = self.iobus.port + self.bridge.slave = self.membus.port self.physmem.port = self.membus.port self.disk0 = CowIdeDisk(driveID='master') self.disk2 = CowIdeDisk(driveID='master') @@ -146,6 +150,10 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None): return self def makeSparcSystem(mem_mode, mdesc = None): + # Constants from iob.cc and uart8250.cc + iob_man_addr = 0x9800000000 + uart_pio_size = 8 + class CowMmDisk(MmDisk): image = CowDiskImage(child=RawDiskImage(read_only=True), read_only=False) @@ -166,8 +174,8 @@ def makeSparcSystem(mem_mode, mdesc = None): self.t1000.attachIO(self.iobus) self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) - self.bridge.side_a = self.iobus.port - self.bridge.side_b = self.membus.port + self.bridge.master = self.iobus.port + self.bridge.slave = self.membus.port self.physmem.port = self.membus.port self.physmem2.port = self.membus.port self.rom.port = self.membus.port @@ -178,6 +186,25 @@ def makeSparcSystem(mem_mode, mdesc = None): self.disk0 = CowMmDisk() self.disk0.childImage(disk('disk.s10hw2')) self.disk0.pio = self.iobus.port + + # The puart0 and hvuart are placed on the IO bus, so create ranges + # for them. The remaining IO range is rather fragmented, so poke + # holes for the iob and partition descriptors etc. + self.bridge.ranges = \ + [ + AddrRange(self.t1000.puart0.pio_addr, + self.t1000.puart0.pio_addr + uart_pio_size - 1), + AddrRange(self.disk0.pio_addr, + self.t1000.fake_jbi.pio_addr + + self.t1000.fake_jbi.pio_size - 1), + AddrRange(self.t1000.fake_clk.pio_addr, + iob_man_addr - 1), + AddrRange(self.t1000.fake_l2_1.pio_addr, + self.t1000.fake_ssi.pio_addr + + self.t1000.fake_ssi.pio_size - 1), + AddrRange(self.t1000.hvuart.pio_addr, + self.t1000.hvuart.pio_addr + uart_pio_size - 1) + ] self.reset_bin = binary('reset_new.bin') self.hypervisor_bin = binary('q_new.bin') self.openboot_bin = binary('openboot_new.bin') @@ -206,8 +233,8 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): self.membus = MemBus(bus_id=1) self.membus.badaddr_responder.warn_access = "warn" self.bridge = Bridge(delay='50ns', nack_delay='4ns') - self.bridge.side_a = self.iobus.port - self.bridge.side_b = self.membus.port + self.bridge.master = self.iobus.port + self.bridge.slave = self.membus.port self.mem_mode = mem_mode @@ -261,7 +288,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): self.boot_osflags = boot_flags self.physmem.port = self.membus.port - self.realview.attachOnChipIO(self.membus) + self.realview.attachOnChipIO(self.membus, self.bridge) self.realview.attachIO(self.iobus) self.intrctrl = IntrControl() self.terminal = Terminal() @@ -287,8 +314,8 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None): self.membus = MemBus(bus_id=1) self.bridge = Bridge(delay='50ns', nack_delay='4ns') self.physmem = PhysicalMemory(range = AddrRange('1GB')) - self.bridge.side_a = self.iobus.port - self.bridge.side_b = self.membus.port + self.bridge.master = self.iobus.port + self.bridge.slave = self.membus.port self.physmem.port = self.membus.port self.disk0 = CowIdeDisk(driveID='master') self.disk2 = CowIdeDisk(driveID='master') @@ -316,14 +343,42 @@ def x86IOAddress(port): return IO_address_space_base + port def connectX86ClassicSystem(x86_sys): + # Constants similar to x86_traits.hh + IO_address_space_base = 0x8000000000000000 + pci_config_address_space_base = 0xc000000000000000 + interrupts_address_space_base = 0xa000000000000000 + APIC_range_size = 1 << 12; + x86_sys.membus = MemBus(bus_id=1) x86_sys.physmem.port = x86_sys.membus.port # North Bridge x86_sys.iobus = Bus(bus_id=0) x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') - x86_sys.bridge.side_a = x86_sys.iobus.port - x86_sys.bridge.side_b = x86_sys.membus.port + x86_sys.bridge.master = x86_sys.iobus.port + x86_sys.bridge.slave = x86_sys.membus.port + # Allow the bridge to pass through the IO APIC (two pages), + # everything in the IO address range up to the local APIC, and + # then the entire PCI address space and beyond + x86_sys.bridge.ranges = \ + [ + AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, + x86_sys.pc.south_bridge.io_apic.pio_addr + + APIC_range_size - 1), + AddrRange(IO_address_space_base, + interrupts_address_space_base - 1), + AddrRange(pci_config_address_space_base, + Addr.max) + ] + + # Create a bridge from the IO bus to the memory bus to allow access to + # the local APIC (two pages) + x86_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns') + x86_sys.iobridge.slave = x86_sys.iobus.port + x86_sys.iobridge.master = x86_sys.membus.port + x86_sys.iobridge.ranges = [AddrRange(interrupts_address_space_base, + interrupts_address_space_base + + APIC_range_size - 1)] # connect the io bus x86_sys.pc.attachIO(x86_sys.iobus) -- cgit v1.2.3 From 55cf3f4ac11668c4da71411a4221cc8c84298b1a Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Tue, 17 Jan 2012 12:55:09 -0600 Subject: MEM: Removing the default port peer from Python ports In preparation for the introduction of Master and Slave ports, this patch removes the default port parameter in the Python port and thus forces the argument list of the Port to contain only the description. The drawback at this point is that the config port and dma port of PCI and DMA devices have to be connected explicitly. This is key for future diversification as the pio and config port are slaves, but the dma port is a master. --- configs/common/FSConfig.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'configs/common') diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 8407db869..6154f9877 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -84,7 +84,11 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): self.tsunami = BaseTsunami() self.tsunami.attachIO(self.iobus) self.tsunami.ide.pio = self.iobus.port + self.tsunami.ide.config = self.iobus.port + self.tsunami.ide.dma = self.iobus.port self.tsunami.ethernet.pio = self.iobus.port + self.tsunami.ethernet.config = self.iobus.port + self.tsunami.ethernet.dma = self.iobus.port self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), read_only = True)) self.intrctrl = IntrControl() @@ -129,7 +133,11 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None): self.tsunami = BaseTsunami() self.tsunami.attachIO(self.piobus) self.tsunami.ide.pio = self.piobus.port + self.tsunami.ide.config = self.piobus.port + self.tsunami.ide.dma = self.piobus.port self.tsunami.ethernet.pio = self.piobus.port + self.tsunami.ethernet.config = self.piobus.port + self.tsunami.ethernet.dma = self.piobus.port # # Store the dma devices for later connection to dma ruby ports. @@ -324,7 +332,11 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None): self.malta = BaseMalta() self.malta.attachIO(self.iobus) self.malta.ide.pio = self.iobus.port + self.malta.ide.config = self.iobus.port + self.malta.ide.dma = self.iobus.port self.malta.ethernet.pio = self.iobus.port + self.malta.ethernet.config = self.iobus.port + self.malta.ethernet.dma = self.iobus.port self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), read_only = True)) self.intrctrl = IntrControl() -- cgit v1.2.3 From 24c23009980a11dfba147fb4ed93329f4dcf4c0d Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Mon, 23 Jan 2012 11:33:52 -0600 Subject: Config: Enable using O3 CPU and Ruby in SE mode --- configs/common/Simulation.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'configs/common') diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 434fe8369..07cc323f9 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -43,7 +43,7 @@ def setCPUClass(options): if options.cpu_type == "timing": class TmpClass(TimingSimpleCPU): pass elif options.cpu_type == "detailed": - if not options.caches: + if not options.caches and not options.ruby: print "O3 CPU must be used with caches" sys.exit(1) class TmpClass(DerivO3CPU): pass -- cgit v1.2.3 From fc7cf40de672fdae5272cb7b69123a44ae274ed6 Mon Sep 17 00:00:00 2001 From: Ronald Dreslinski Date: Thu, 26 Jan 2012 14:53:48 -0500 Subject: configs: A more realistic configuration of an ARM-like processor --- configs/common/CacheConfig.py | 29 +++++++++++++++++++++++------ configs/common/Options.py | 3 ++- configs/common/Simulation.py | 8 ++++++-- 3 files changed, 31 insertions(+), 9 deletions(-) (limited to 'configs/common') diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 00517dfc4..364b20f28 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -32,11 +32,17 @@ import m5 from m5.objects import * from Caches import * +from O3_ARM_v7a import * def config_cache(options, system): if options.l2cache: - system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc, - block_size=options.cacheline_size) + if options.cpu_type == "arm_detailed": + system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc, + block_size=options.cacheline_size) + else: + system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc, + block_size=options.cacheline_size) + system.tol2bus = Bus() system.l2.cpu_side = system.tol2bus.port system.l2.mem_side = system.membus.port @@ -44,10 +50,21 @@ def config_cache(options, system): for i in xrange(options.num_cpus): if options.caches: - icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, - block_size=options.cacheline_size) - dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, - block_size=options.cacheline_size) + if options.cpu_type == "arm_detailed": + icache = O3_ARM_v7a_ICache(size = options.l1i_size, + assoc = options.l1i_assoc, + block_size=options.cacheline_size) + dcache = O3_ARM_v7a_DCache(size = options.l1d_size, + assoc = options.l1d_assoc, + block_size=options.cacheline_size) + else: + icache = L1Cache(size = options.l1i_size, + assoc = options.l1i_assoc, + block_size=options.cacheline_size) + dcache = L1Cache(size = options.l1d_size, + assoc = options.l1d_assoc, + block_size=options.cacheline_size) + if buildEnv['TARGET_ISA'] == 'x86': system.cpu[i].addPrivateSplitL1Caches(icache, dcache, PageTableWalkerCache(), diff --git a/configs/common/Options.py b/configs/common/Options.py index 1941875bc..0932f2629 100644 --- a/configs/common/Options.py +++ b/configs/common/Options.py @@ -28,7 +28,8 @@ # system options parser.add_option("--cpu-type", type="choice", default="atomic", - choices = ["atomic", "timing", "detailed", "inorder"], + choices = ["atomic", "timing", "detailed", "inorder", + "arm_detailed"], help = "type of cpu to run with") parser.add_option("-n", "--num-cpus", type="int", default=1) parser.add_option("--caches", action="store_true") diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 07cc323f9..193f8d487 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -34,6 +34,7 @@ import m5 from m5.defines import buildEnv from m5.objects import * from m5.util import * +from O3_ARM_v7a import * addToPath('../common') @@ -42,11 +43,14 @@ def setCPUClass(options): atomic = False if options.cpu_type == "timing": class TmpClass(TimingSimpleCPU): pass - elif options.cpu_type == "detailed": + elif options.cpu_type == "detailed" or options.cpu_type == "arm_detailed": if not options.caches and not options.ruby: print "O3 CPU must be used with caches" sys.exit(1) - class TmpClass(DerivO3CPU): pass + if options.cpu_type == "arm_detailed": + class TmpClass(O3_ARM_v7a_3): pass + else: + class TmpClass(DerivO3CPU): pass elif options.cpu_type == "inorder": if not options.caches: print "InOrder CPU must be used with caches" -- cgit v1.2.3 From 38ee552798ff2fe987e24a2e070edb96c9d486af Mon Sep 17 00:00:00 2001 From: Ronald Dreslinski Date: Thu, 26 Jan 2012 16:44:43 -0500 Subject: configs: actually add ARMv7a-like cpu/cache file --- configs/common/O3_ARM_v7a.py | 199 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 199 insertions(+) create mode 100644 configs/common/O3_ARM_v7a.py (limited to 'configs/common') diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py new file mode 100644 index 000000000..a2b769f27 --- /dev/null +++ b/configs/common/O3_ARM_v7a.py @@ -0,0 +1,199 @@ +# Copyright (c) 2012 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + + +from m5.objects import * + +# Simple ALU Instructions have a latency of 1 +class O3_ARM_v7a_Simple_Int(FUDesc): + opList = [ OpDesc(opClass='IntAlu', opLat=1) ] + count = 2 + +# Complex ALU instructions have a variable latencies +class O3_ARM_v7a_Complex_Int(FUDesc): + opList = [ OpDesc(opClass='IntMult', opLat=3, issueLat=1), + OpDesc(opClass='IntDiv', opLat=12, issueLat=12), + OpDesc(opClass='IprAccess', opLat=3, issueLat=1) ] + count = 1 + + +# Floating point and SIMD instructions +class O3_ARM_v7a_FP(FUDesc): + opList = [ OpDesc(opClass='SimdAdd', opLat=4), + OpDesc(opClass='SimdAddAcc', opLat=4), + OpDesc(opClass='SimdAlu', opLat=4), + OpDesc(opClass='SimdCmp', opLat=4), + OpDesc(opClass='SimdCvt', opLat=3), + OpDesc(opClass='SimdMisc', opLat=3), + OpDesc(opClass='SimdMult',opLat=5), + OpDesc(opClass='SimdMultAcc',opLat=5), + OpDesc(opClass='SimdShift',opLat=3), + OpDesc(opClass='SimdShiftAcc', opLat=3), + OpDesc(opClass='SimdSqrt', opLat=9), + OpDesc(opClass='SimdFloatAdd',opLat=5), + OpDesc(opClass='SimdFloatAlu',opLat=5), + OpDesc(opClass='SimdFloatCmp', opLat=3), + OpDesc(opClass='SimdFloatCvt', opLat=3), + OpDesc(opClass='SimdFloatDiv', opLat=3), + OpDesc(opClass='SimdFloatMisc', opLat=3), + OpDesc(opClass='SimdFloatMult', opLat=3), + OpDesc(opClass='SimdFloatMultAcc',opLat=1), + OpDesc(opClass='SimdFloatSqrt', opLat=9), + OpDesc(opClass='FloatAdd', opLat=5), + OpDesc(opClass='FloatCmp', opLat=5), + OpDesc(opClass='FloatCvt', opLat=5), + OpDesc(opClass='FloatDiv', opLat=9, issueLat=9), + OpDesc(opClass='FloatSqrt', opLat=33, issueLat=33), + OpDesc(opClass='FloatMult', opLat=4) ] + count = 2 + + +# Load/Store Units +class O3_ARM_v7a_Load(FUDesc): + opList = [ OpDesc(opClass='MemRead',opLat=2) ] + count = 1 + +class O3_ARM_v7a_Store(FUDesc): + opList = [OpDesc(opClass='MemWrite',opLat=2) ] + count = 1 + +# Functional Units for this CPU +class O3_ARM_v7a_FUP(FUPool): + FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(), + O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()] + + +class O3_ARM_v7a_3(DerivO3CPU): + predType = "tournament" + localPredictorSize = 64 + localCtrBits = 2 + localHistoryTableSize = 64 + localHistoryBits = 6 + globalPredictorSize = 8192 + globalCtrBits = 2 + globalHistoryBits = 13 + choicePredictorSize = 8192 + choiceCtrBits = 2 + BTBEntries = 2048 + BTBTagSize = 18 + RASSize = 16 + instShiftAmt = 2 + LQEntries = 16 + SQEntries = 16 + LSQDepCheckShift = 0 + LFSTSize = 1024 + SSITSize = 1024 + decodeToFetchDelay = 1 + renameToFetchDelay = 1 + iewToFetchDelay = 1 + commitToFetchDelay = 1 + renameToDecodeDelay = 1 + iewToDecodeDelay = 1 + commitToDecodeDelay = 1 + iewToRenameDelay = 1 + commitToRenameDelay = 1 + commitToIEWDelay = 1 + fetchWidth = 3 + fetchToDecodeDelay = 3 + decodeWidth = 3 + decodeToRenameDelay = 2 + renameWidth = 3 + renameToIEWDelay = 1 + issueToExecuteDelay = 1 + dispatchWidth = 6 + issueWidth = 8 + wbWidth = 8 + wbDepth = 1 + fuPool = O3_ARM_v7a_FUP() + iewToCommitDelay = 1 + renameToROBDelay = 1 + commitWidth = 8 + squashWidth = 8 + trapLatency = 13 + backComSize = 5 + forwardComSize = 5 + numPhysIntRegs = 128 + numPhysFloatRegs = 128 + numIQEntries = 32 + numROBEntries = 40 + + defer_registration= False + +# Instruction Cache +# All latencys assume a 1GHz clock rate, with a faster clock they would be faster +class O3_ARM_v7a_ICache(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 2 + tgts_per_mshr = 8 + size = '32kB' + assoc = 2 + is_top_level = 'true' + +# Data Cache +# All latencys assume a 1GHz clock rate, with a faster clock they would be faster +class O3_ARM_v7a_DCache(BaseCache): + latency = '2ns' + block_size = 64 + mshrs = 6 + tgts_per_mshr = 8 + size = '32kB' + assoc = 2 + write_buffers = 16 + is_top_level = 'true' + +# TLB Cache +# Use a cache as a L2 TLB +class O3_ARM_v7aWalkCache(BaseCache): + latency = '4ns' + block_size = 64 + mshrs = 6 + tgts_per_mshr = 8 + size = '1kB' + assoc = 8 + write_buffers = 16 + is_top_level = 'true' + + +# L2 Cache +# All latencys assume a 1GHz clock rate, with a faster clock they would be faster +class O3_ARM_v7aL2(BaseCache): + latency = '12ns' + block_size = 64 + mshrs = 16 + tgts_per_mshr = 8 + size = '1MB' + assoc = 16 + write_buffers = 8 + # Simple stride prefetcher + prefetch_policy = 'stride' + prefetch_on_access = 'true' + prefetch_latency = '1.0ns' + prefetch_degree = 8 + + -- cgit v1.2.3