From 36dc93a5fa09765b9d2bac402bb557d228effcad Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 2 Mar 2015 04:00:47 -0500 Subject: mem: Move crossbar default latencies to subclasses This patch introduces a few subclasses to the CoherentXBar and NoncoherentXBar to distinguish the different uses in the system. We use the crossbar in a wide range of places: interfacing cores to the L2, as a system interconnect, connecting I/O and peripherals, etc. Needless to say, these crossbars have very different performance, and the clock frequency alone is not enough to distinguish these scenarios. Instead of trying to capture every possible case, this patch introduces dedicated subclasses for the three primary use-cases: L2XBar, SystemXBar and IOXbar. More can be added if needed, and the defaults can be overridden. --- configs/dram/sweep.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'configs/dram') diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py index 18a58b2da..f0b20dcc5 100644 --- a/configs/dram/sweep.py +++ b/configs/dram/sweep.py @@ -84,7 +84,7 @@ if args: # start with the system itself, using a multi-layer 1.5 GHz # crossbar, delivering 64 bytes / 5 cycles (one header cycle) # which amounts to 19.2 GByte/s per layer and thus per port -system = System(membus = NoncoherentXBar(width = 16)) +system = System(membus = IOXBar(width = 16)) system.clk_domain = SrcClockDomain(clock = '1.5GHz', voltage_domain = VoltageDomain(voltage = '1V')) -- cgit v1.2.3