From 5bf2a86c6a8a1fc68422053e1a782d3efe0e6f3c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pierre-Yves=20P=C3=A9neau?= Date: Wed, 22 Mar 2017 18:36:13 +0100 Subject: arm, config: added support for ex5 model of big.LITTLE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch enables using calibrated big and LITTLE cores, ex5_big and ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5 model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory hierarchy latencies have been calibrated using the lmbench micro-benchmark suite. The preliminary validation results have been published as: 'Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration', in International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016). From http://reviews.gem5.org/r/3666 Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Signed-off-by: Anastasiia Butko Signed-off-by: Pierre-Yves Péneau Reviewed-on: https://gem5-review.googlesource.com/2464 Reviewed-by: Gabor Dozsa Maintainer: Jason Lowe-Power --- configs/example/arm/fs_bigLITTLE.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'configs/example/arm') diff --git a/configs/example/arm/fs_bigLITTLE.py b/configs/example/arm/fs_bigLITTLE.py index d6825dfaa..3e7ac2f76 100644 --- a/configs/example/arm/fs_bigLITTLE.py +++ b/configs/example/arm/fs_bigLITTLE.py @@ -51,6 +51,8 @@ m5.util.addToPath("../../") from common import SysPaths from common import CpuConfig +from common import ex5_big +from common import ex5_LITTLE import devices from devices import AtomicCluster, KvmCluster @@ -95,6 +97,21 @@ class LittleCluster(devices.CpuCluster): super(LittleCluster, self).__init__(system, num_cpus, cpu_clock, cpu_voltage, *cpu_config) +class Ex5BigCluster(devices.CpuCluster): + def __init__(self, system, num_cpus, cpu_clock, + cpu_voltage="1.0V"): + cpu_config = [ CpuConfig.get("ex5_big"), ex5_big.L1I, ex5_big.L1D, + ex5_big.WalkCache, ex5_big.L2 ] + super(Ex5BigCluster, self).__init__(system, num_cpus, cpu_clock, + cpu_voltage, *cpu_config) + +class Ex5LittleCluster(devices.CpuCluster): + def __init__(self, system, num_cpus, cpu_clock, + cpu_voltage="1.0V"): + cpu_config = [ CpuConfig.get("ex5_LITTLE"), ex5_LITTLE.L1I, + ex5_LITTLE.L1D, ex5_LITTLE.WalkCache, ex5_LITTLE.L2 ] + super(Ex5LittleCluster, self).__init__(system, num_cpus, cpu_clock, + cpu_voltage, *cpu_config) def createSystem(caches, kernel, bootscript, disks=[]): sys = devices.SimpleSystem(caches, default_mem_size, @@ -127,6 +144,7 @@ def createSystem(caches, kernel, bootscript, disks=[]): cpu_types = { "atomic" : (AtomicCluster, AtomicCluster), "timing" : (BigCluster, LittleCluster), + "exynos" : (Ex5BigCluster, Ex5LittleCluster), } # Only add the KVM CPU if it has been compiled into gem5 -- cgit v1.2.3