From b5cc4c760478240bf8c5f7de977bf2b56fd8dfd4 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Thu, 20 Mar 2014 09:14:14 -0500 Subject: config: ruby: rename _cpu_ruby_ports to _cpu_ports --- configs/example/fs.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'configs/example/fs.py') diff --git a/configs/example/fs.py b/configs/example/fs.py index 6c71ef432..584748299 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -149,18 +149,18 @@ def build_test_system(np): cpu.createThreads() cpu.createInterruptController() - cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave - cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave + cpu.icache_port = test_sys.ruby._cpu_ports[i].slave + cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] == "x86": - cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave - cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave + cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave + cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave - cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master - cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave - cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master + cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master + cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave + cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master - test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True + test_sys.ruby._cpu_ports[i].access_phys_mem = True # Create the appropriate memory controllers # and connect them to the IO bus -- cgit v1.2.3