From ca0fd665dcf6a4aeda07955d3898b03204c88fd8 Mon Sep 17 00:00:00 2001 From: Wendy Elsasser Date: Tue, 14 Feb 2017 15:09:18 -0600 Subject: mem: Update DRAM configuration names Names of DRAM configurations were updated to reflect both the channel and device data width. Previous naming format was: __ The following nomenclature is now used: __x where n = The number of devices per rank on the channel x = Device width Total channel width can be calculated by n*w Example: A 64-bit DDR4, 2400 channel consisting of 4-bit devices: n = 16 w = 4 The resulting configuration name is: DDR4_2400_16x4 Updated scripts to match new naming convention. Added unique configurations for DDR4 for: 1) 16x4 2) 8x8 3) 4x16 Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1 Reviewed-by: Radhika Jagtap Reviewed-by: Curtis Dunham --- configs/example/memcheck.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'configs/example/memcheck.py') diff --git a/configs/example/memcheck.py b/configs/example/memcheck.py index 7ef413389..0bbcd2f7c 100644 --- a/configs/example/memcheck.py +++ b/configs/example/memcheck.py @@ -216,7 +216,7 @@ cfg_file.close() proto_tester = TrafficGen(config_file = cfg_file_name) # Set up the system along with a DRAM controller -system = System(physmem = DDR3_1600_x64()) +system = System(physmem = DDR3_1600_8x8()) system.voltage_domain = VoltageDomain(voltage = '1V') -- cgit v1.2.3