From f00cba34eb8e6bf947721f72de314f4e8bd6a8f8 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 12 Jul 2012 12:56:13 -0400 Subject: Mem: Make SimpleMemory single ported This patch changes the simple memory to have a single slave port rather than a vector port. The simple memory makes no attempts at modelling the contention between multiple ports, and any such multiplexing and demultiplexing could be done in a bus (or crossbar) outside the memory controller. This scenario also matches with the ongoing work on a SimpleDRAM model, which will be a single-ported single-channel controller that can be used in conjunction with a bus (or crossbar) to create a multi-port multi-channel controller. There are only very few regressions that make use of the vector port, and these are all for functional accesses only. To facilitate these cases, memtest and memtest-ruby have been updated to also have a "functional" bus to perform the (de)multiplexing of the functional memory accesses. --- configs/example/memtest.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'configs/example/memtest.py') diff --git a/configs/example/memtest.py b/configs/example/memtest.py index 590378920..4f57ef063 100644 --- a/configs/example/memtest.py +++ b/configs/example/memtest.py @@ -141,6 +141,7 @@ for scale in treespec[:-2]: # system simulated system = System(funcmem = SimpleMemory(in_addr_map = False), + funcbus = NoncoherentBus(), physmem = SimpleMemory(latency = "100ns")) def make_level(spec, prototypes, attach_obj, attach_port): @@ -169,10 +170,13 @@ def make_level(spec, prototypes, attach_obj, attach_port): parent.cpu = objs for t in objs: t.test = getattr(attach_obj, attach_port) - t.functional = system.funcmem.port + t.functional = system.funcbus.slave make_level(treespec, prototypes, system.physmem, "port") +# connect reference memory to funcbus +system.funcbus.master = system.funcmem.port + # ----------------------- # run simulation # ----------------------- -- cgit v1.2.3