From 580c8421ab5d438ea4264a3a44495568a38bc59b Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Mon, 30 Oct 2006 16:51:46 -0500 Subject: se.py, fs.py: import Caches Simulation.py: Fix typo - L2Cache --> L1Cache configs/common/Simulation.py: Fix typo - L2Cache --> L1Cache configs/example/fs.py: configs/example/se.py: import Caches --HG-- extra : convert_revision : 4292225b322c069665262eab7c83b5341844fba0 --- configs/example/se.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'configs/example/se.py') diff --git a/configs/example/se.py b/configs/example/se.py index 1afeaf391..83c2b1f8d 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -35,11 +35,16 @@ from m5.objects import * import os, optparse, sys m5.AddToPath('../common') import Simulation +from Caches import * # Get paths we might need. It's expected this file is in m5/configs/example. config_path = os.path.dirname(os.path.abspath(__file__)) config_root = os.path.dirname(config_path) m5_root = os.path.dirname(config_root) +print m5_root +print config_path +print config_root + parser = optparse.OptionParser() @@ -111,7 +116,7 @@ system.physmem.port = system.membus.port for i in xrange(np): if options.caches and not options.standard_switch: system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L2Cache(size = '64kB')) + L1Cache(size = '64kB')) system.cpu[i].connectMemPorts(system.membus) system.cpu[i].mem = system.physmem system.cpu[i].workload = process -- cgit v1.2.3