From 3022d463fbe1f969aadf7284ade996539c9454f9 Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Thu, 6 Nov 2014 05:42:21 -0600
Subject: ruby: interface with classic memory controller This patch is the
 final in the series.  The whole series and this patch in particular were
 written with the aim of interfacing ruby's directory controller with the
 memory controller in the classic memory system.  This is being done since
 ruby's memory controller has not being kept up to date with the changes going
 on in DRAMs.  Classic's memory controller is more up to date and supports
 multiple different types of DRAM.  This also brings classic and ruby ever
 more close.  The patch also changes ruby's memory controller to expose the
 same interface.

---
 configs/example/fs.py               |  2 --
 configs/example/ruby_direct_test.py | 20 ++++++--------------
 configs/example/ruby_mem_test.py    |  1 -
 configs/example/ruby_random_test.py |  3 +--
 configs/example/se.py               |  5 -----
 5 files changed, 7 insertions(+), 24 deletions(-)

(limited to 'configs/example')

diff --git a/configs/example/fs.py b/configs/example/fs.py
index abf8fe966..727f69339 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -137,8 +137,6 @@ def build_test_system(np):
 
         Ruby.create_system(options, True, test_sys, test_sys.iobus,
                            test_sys._dma_ports)
-        test_sys.physmem = [SimpleMemory(range = r, null = True)
-                          for r in test_sys.mem_ranges]
 
         # Create a seperate clock domain for Ruby
         test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py
index 6773aea6d..857909ba9 100644
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -48,7 +48,7 @@ m5_root = os.path.dirname(config_root)
 parser = optparse.OptionParser()
 Options.addCommonOptions(parser)
 
-parser.add_option("-l", "--requests", metavar="N", default=100,
+parser.add_option("--requests", metavar="N", default=100,
                   help="Stop after N requests")
 parser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
                   help="Wakeup every N cycles")
@@ -87,13 +87,8 @@ else:
     print "Error: unknown direct test generator"
     sys.exit(1)
 
-#
-# Create the M5 system.  Note that the Memory Object isn't
-# actually used by the rubytester, but is included to support the
-# M5 memory size == Ruby memory size checks
-#
-system = System(physmem = SimpleMemory(),
-                mem_ranges = [AddrRange(options.mem_size)])
+# Create the M5 system.
+system = System(mem_ranges = [AddrRange(options.mem_size)])
 
 
 # Create a top-level voltage domain and clock domain
@@ -102,12 +97,9 @@ system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
                                    voltage_domain = system.voltage_domain)
 
-#
 # Create the ruby random tester
-#
-system.cpu = RubyDirectedTester(requests_to_complete = \
-                                   options.requests,
-                                   generator = generator)
+system.cpu = RubyDirectedTester(requests_to_complete = options.requests,
+                                generator = generator)
 
 Ruby.create_system(options, False, system)
 
@@ -121,7 +113,7 @@ for ruby_port in system.ruby._cpu_ports:
     #
     # Tie the ruby tester ports to the ruby cpu ports
     #
-    system.tester.cpuPort = ruby_port.slave
+    system.cpu.cpuPort = ruby_port.slave
 
 # -----------------------
 # run simulation
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index 15684d153..f5e6d2a82 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -107,7 +107,6 @@ cpus = [ MemTest(atomic = False,
 system = System(cpu = cpus,
                 funcmem = SimpleMemory(in_addr_map = False),
                 funcbus = NoncoherentXBar(),
-                physmem = SimpleMemory(),
                 clk_domain = SrcClockDomain(clock = options.sys_clock),
                 mem_ranges = [AddrRange(options.mem_size)])
 
diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py
index 7cde5b86c..225b3d23b 100644
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -97,8 +97,7 @@ tester = RubyTester(check_flush = check_flush,
 # actually used by the rubytester, but is included to support the
 # M5 memory size == Ruby memory size checks
 #
-system = System(cpu = tester, physmem = SimpleMemory(),
-                mem_ranges = [AddrRange(options.mem_size)])
+system = System(cpu = tester, mem_ranges = [AddrRange(options.mem_size)])
 
 # Create a top-level voltage domain and clock domain
 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
diff --git a/configs/example/se.py b/configs/example/se.py
index 461ebf11c..e0535c726 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -225,11 +225,6 @@ if options.ruby:
         print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
         sys.exit(1)
 
-    # Use SimpleMemory with the null option since this memory is only used
-    # for determining which addresses are within the range of the memory.
-    # No space allocation is required.
-    system.physmem = SimpleMemory(range=AddrRange(options.mem_size),
-                              null = True)
     options.use_map = True
     Ruby.create_system(options, False, system)
     assert(options.num_cpus == len(system.ruby._cpu_ports))
-- 
cgit v1.2.3