From a5c4eb3de9deb3a71a6a5230a25ff5962e584980 Mon Sep 17 00:00:00 2001 From: Mitch Hayenga Date: Wed, 30 Sep 2015 11:14:19 -0500 Subject: isa,cpu: Add support for FS SMT Interrupts Adds per-thread interrupt controllers and thread/context logic so that interrupts properly get routed in SMT systems. --- configs/example/fs.py | 6 +++--- configs/example/se.py | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'configs/example') diff --git a/configs/example/fs.py b/configs/example/fs.py index 70a3b950e..9d8b87aaa 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -176,9 +176,9 @@ def build_test_system(np): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave - cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master - cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave - cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master + cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master + cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave + cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master else: if options.caches or options.l2cache: diff --git a/configs/example/se.py b/configs/example/se.py index afd916cdb..0928482b7 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -265,9 +265,9 @@ if options.ruby: system.cpu[i].icache_port = ruby_port.slave system.cpu[i].dcache_port = ruby_port.slave if buildEnv['TARGET_ISA'] == 'x86': - system.cpu[i].interrupts.pio = ruby_port.master - system.cpu[i].interrupts.int_master = ruby_port.slave - system.cpu[i].interrupts.int_slave = ruby_port.master + system.cpu[i].interrupts[0].pio = ruby_port.master + system.cpu[i].interrupts[0].int_master = ruby_port.slave + system.cpu[i].interrupts[0].int_slave = ruby_port.master system.cpu[i].itb.walker.port = ruby_port.slave system.cpu[i].dtb.walker.port = ruby_port.slave else: -- cgit v1.2.3