From dd6a21190e33f6d09ee6ff5ed045f92000c5e801 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 5 Sep 2007 14:57:50 -0400 Subject: Configuration: Fix example script to only create one L2 if --l2cache and -nX are given as parameters. Patch submitted by: Jonas Diemer [diemer (a) ida.ing.tu-bs.de] --HG-- extra : convert_revision : 1dfc548d2bc33d622d829bbf385f4bf9700711cd --- configs/example/se.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'configs/example') diff --git a/configs/example/se.py b/configs/example/se.py index 639bcd7c6..b4b50a013 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -100,15 +100,17 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], system.physmem.port = system.membus.port +if options.l2cache: + system.l2 = L2Cache(size='2MB') + system.tol2bus = Bus() + system.l2.cpu_side = system.tol2bus.port + system.l2.mem_side = system.membus.port + for i in xrange(np): if options.caches: system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) if options.l2cache: - system.l2 = L2Cache(size='2MB') - system.tol2bus = Bus() - system.l2.cpu_side = system.tol2bus.port - system.l2.mem_side = system.membus.port system.cpu[i].connectMemPorts(system.tol2bus) else: system.cpu[i].connectMemPorts(system.membus) -- cgit v1.2.3