From ca0fd665dcf6a4aeda07955d3898b03204c88fd8 Mon Sep 17 00:00:00 2001 From: Wendy Elsasser Date: Tue, 14 Feb 2017 15:09:18 -0600 Subject: mem: Update DRAM configuration names Names of DRAM configurations were updated to reflect both the channel and device data width. Previous naming format was: __ The following nomenclature is now used: __x where n = The number of devices per rank on the channel x = Device width Total channel width can be calculated by n*w Example: A 64-bit DDR4, 2400 channel consisting of 4-bit devices: n = 16 w = 4 The resulting configuration name is: DDR4_2400_16x4 Updated scripts to match new naming convention. Added unique configurations for DDR4 for: 1) 16x4 2) 8x8 3) 4x16 Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1 Reviewed-by: Radhika Jagtap Reviewed-by: Curtis Dunham --- configs/learning_gem5/part1/simple.py | 2 +- configs/learning_gem5/part1/two_level.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'configs/learning_gem5') diff --git a/configs/learning_gem5/part1/simple.py b/configs/learning_gem5/part1/simple.py index 1249a8464..393240a66 100644 --- a/configs/learning_gem5/part1/simple.py +++ b/configs/learning_gem5/part1/simple.py @@ -75,7 +75,7 @@ if m5.defines.buildEnv['TARGET_ISA'] == "x86": system.cpu.interrupts[0].int_slave = system.membus.master # Create a DDR3 memory controller and connect it to the membus -system.mem_ctrl = DDR3_1600_x64() +system.mem_ctrl = DDR3_1600_8x8() system.mem_ctrl.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master diff --git a/configs/learning_gem5/part1/two_level.py b/configs/learning_gem5/part1/two_level.py index 878baa312..3dcb71a51 100644 --- a/configs/learning_gem5/part1/two_level.py +++ b/configs/learning_gem5/part1/two_level.py @@ -128,7 +128,7 @@ if m5.defines.buildEnv['TARGET_ISA'] == "x86": system.system_port = system.membus.slave # Create a DDR3 memory controller -system.mem_ctrl = DDR3_1600_x64() +system.mem_ctrl = DDR3_1600_8x8() system.mem_ctrl.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master -- cgit v1.2.3