From ce2722cdd97a31f85d36f6c32637b230e3c25c73 Mon Sep 17 00:00:00 2001 From: Sophiane Senni Date: Wed, 30 Nov 2016 17:10:27 -0500 Subject: mem: Split the hit_latency into tag_latency and data_latency If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Signed-off-by: Jason Lowe-Power --- configs/learning_gem5/part1/caches.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'configs/learning_gem5') diff --git a/configs/learning_gem5/part1/caches.py b/configs/learning_gem5/part1/caches.py index 87256e5d0..74999cd57 100644 --- a/configs/learning_gem5/part1/caches.py +++ b/configs/learning_gem5/part1/caches.py @@ -45,7 +45,8 @@ class L1Cache(Cache): """Simple L1 Cache with default values""" assoc = 2 - hit_latency = 2 + tag_latency = 2 + data_latency = 2 response_latency = 2 mshrs = 4 tgts_per_mshr = 20 @@ -107,7 +108,8 @@ class L2Cache(Cache): # Default parameters size = '256kB' assoc = 8 - hit_latency = 20 + tag_latency = 20 + data_latency = 20 response_latency = 20 mshrs = 20 tgts_per_mshr = 12 -- cgit v1.2.3