From 40bcbf42539fec83628f2ae2627238adff27f62c Mon Sep 17 00:00:00 2001 From: Brad Beckmann Date: Thu, 28 Apr 2011 17:18:14 -0700 Subject: network: convert links & switches to first class C++ SimObjects This patch converts links and switches from second class simobjects that were virtually ignored by the networks (both simple and Garnet) to first class simobjects that directly correspond to c++ ojbects manipulated by the topology and network classes. This is especially true for Garnet, where the links and switches directly correspond to specific C++ objects. By making this change, many aspects of the Topology class were simplified. --HG-- rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/BasicLink.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/BasicLink.hh rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py --- configs/ruby/MI_example.py | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'configs/ruby/MI_example.py') diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py index 062748eef..5f5703d4e 100644 --- a/configs/ruby/MI_example.py +++ b/configs/ruby/MI_example.py @@ -62,6 +62,8 @@ def create_system(options, system, piobus, dma_devices): # controller constructors are called before the network constructor # block_size_bits = int(math.log(options.cacheline_size, 2)) + + cntrl_count = 0 for i in xrange(options.num_cpus): # @@ -86,6 +88,7 @@ def create_system(options, system, piobus, dma_devices): cpu_seq.pio_port = piobus.port l1_cntrl = L1Cache_Controller(version = i, + cntrl_id = cntrl_count, sequencer = cpu_seq, cacheMemory = cache) @@ -96,6 +99,8 @@ def create_system(options, system, piobus, dma_devices): cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) + cntrl_count += 1 + phys_mem_size = long(system.physmem.range.second) - \ long(system.physmem.range.first) + 1 mem_module_size = phys_mem_size / options.num_dirs @@ -111,6 +116,7 @@ def create_system(options, system, piobus, dma_devices): dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, + cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory( \ version = i, @@ -123,6 +129,8 @@ def create_system(options, system, piobus, dma_devices): exec("system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) + cntrl_count += 1 + for i, dma_device in enumerate(dma_devices): # # Create the Ruby objects associated with the dma controller @@ -132,6 +140,7 @@ def create_system(options, system, piobus, dma_devices): physmem = system.physmem) dma_cntrl = DMA_Controller(version = i, + cntrl_id = cntrl_count, dma_sequencer = dma_seq) exec("system.dma_cntrl%d = dma_cntrl" % i) @@ -142,6 +151,8 @@ def create_system(options, system, piobus, dma_devices): dma_cntrl.dma_sequencer.port = dma_device.dma dma_cntrl_nodes.append(dma_cntrl) + cntrl_count += 1 + all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) -- cgit v1.2.3