From 6cf9f182f678e4ddf2a2b98a5093a7418353217c Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson@arm.com>
Date: Tue, 14 Feb 2012 14:15:30 -0500
Subject: MEM: Fix residual bus ports and make them master/slave

This patch cleans up a number of remaining uses of bus.port which
is now split into bus.master and bus.slave. The only non-trivial change
is the memtest where the level building now has to be aware of the role
of the ports used in the previous level.
---
 configs/splash2/cluster.py | 14 +++++++-------
 configs/splash2/run.py     |  8 ++++----
 2 files changed, 11 insertions(+), 11 deletions(-)

(limited to 'configs/splash2')

diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py
index 4a9446794..a6244a9ef 100644
--- a/configs/splash2/cluster.py
+++ b/configs/splash2/cluster.py
@@ -221,19 +221,19 @@ system.l2 = L2(size = options.l2size, assoc = 8)
 # Connect the L2 cache and memory together
 # ----------------------
 
-system.physmem.port = system.membus.port
-system.l2.cpu_side = system.toL2bus.port
-system.l2.mem_side = system.membus.port
+system.physmem.port = system.membus.master
+system.l2.cpu_side = system.toL2bus.slave
+system.l2.mem_side = system.membus.master
 
 # ----------------------
 # Connect the L2 cache and clusters together
 # ----------------------
 for cluster in clusters:
-    cluster.l1.cpu_side = cluster.clusterbus.port
-    cluster.l1.mem_side = system.toL2bus.port
+    cluster.l1.cpu_side = cluster.clusterbus.master
+    cluster.l1.mem_side = system.toL2bus.slave
     for cpu in cluster.cpus:
-        cpu.icache_port = cluster.clusterbus.port
-        cpu.dcache_port = cluster.clusterbus.port
+        cpu.icache_port = cluster.clusterbus.slave
+        cpu.dcache_port = cluster.clusterbus.slave
 
 # ----------------------
 # Define the root
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 23e986b09..2681a222d 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -207,10 +207,10 @@ system.l2 = L2(size = options.l2size, assoc = 8)
 # Connect the L2 cache and memory together
 # ----------------------
 
-system.physmem.port = system.membus.port
-system.l2.cpu_side = system.toL2bus.port
-system.l2.mem_side = system.membus.port
-system.system_port = system.membus.port
+system.physmem.port = system.membus.master
+system.l2.cpu_side = system.toL2bus.master
+system.l2.mem_side = system.membus.slave
+system.system_port = system.membus.slave
 
 # ----------------------
 # Connect the L2 cache and clusters together
-- 
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