From 06a9f58c68b621f082d39299bdb01f59ef68ef0e Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Fri, 10 Aug 2007 16:14:01 -0400
Subject: DMA: Add IOCache and fix bus bridge to optionally only send requests
 one way so a cache can handle partial block requests for i/o devices.

--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
---
 configs/common/Caches.py   | 7 +++++++
 configs/common/FSConfig.py | 2 +-
 configs/example/fs.py      | 7 ++++++-
 3 files changed, 14 insertions(+), 2 deletions(-)

(limited to 'configs')

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 43a1c6378..f1ea957b5 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -43,3 +43,10 @@ class L2Cache(BaseCache):
     mshrs = 20
     tgts_per_mshr = 12
 
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '10ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 6bcdafb14..9778be3f1 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -53,7 +53,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
     self.readfile = mdesc.script()
     self.iobus = Bus(bus_id=0)
     self.membus = Bus(bus_id=1)
-    self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns')
+    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
     self.bridge.side_a = self.iobus.port
     self.bridge.side_b = self.membus.port
diff --git a/configs/example/fs.py b/configs/example/fs.py
index e772a3ab1..ca1408970 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -121,7 +121,12 @@ for i in xrange(np):
     if options.caches:
         test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                                 L1Cache(size = '64kB'))
-
+        test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+        test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+        test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
+                           cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
+        test_sys.iocache.cpu_side = test_sys.iobus.port
+        test_sys.iocache.mem_side = test_sys.membus.port
     if options.l2cache:
         test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
     else:
-- 
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