From 223e48e6ae651e6e99bc1fbb58ec30d7f88a6e32 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 12 Jan 2008 06:39:15 -0500 Subject: X86: Make the IO ports work using extra physical address lines. Add a serial port. --HG-- extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6 --- configs/common/FSConfig.py | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) (limited to 'configs') diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 5b21dbb39..c8916841b 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2006-2008 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -155,6 +155,10 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None): return self +def x86IOAddress(port): + IO_address_space_base = 0x1000000000000000 + return IO_address_space_base + port; + def makeLinuxX86System(mem_mode, mdesc = None): self = LinuxX86System() if not mdesc: @@ -163,10 +167,23 @@ def makeLinuxX86System(mem_mode, mdesc = None): self.readfile = mdesc.script() # Physical memory - self.membus = Bus(bus_id=0) + self.membus = Bus(bus_id=1) self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) self.physmem.port = self.membus.port + # North Bridge + self.iobus = Bus(bus_id=0) + self.bridge = Bridge(delay='50ns', nack_delay='4ns') + self.bridge.side_a = self.iobus.port + self.bridge.side_b = self.membus.port + + # Serial port and console + self.console = SimConsole() + self.com_1 = Uart8250() + self.com_1.pio_addr = x86IOAddress(0x3f8) + self.com_1.pio = self.iobus.port + self.com_1.sim_console = self.console + # Platform self.opteron = Opteron() -- cgit v1.2.3