From 309e1d81939c44f6b31795be84868605e05b09ec Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 16 May 2006 17:36:50 -0400 Subject: Split SimpleCPU into two different models, AtomicSimpleCPU and TimingSimpleCPU, which use atomic and timing memory accesses respectively. Common code is factored into the BaseSimpleCPU class. AtomicSimpleCPU includes an option (simulate_stalls) to add delays based on the estimated latency reported by the atomic accesses. Plain old "SimpleCPU" is gone; I have not updated all the config files (just test/test.py). Also fixes to get timing accesses working in new memory model and to get split-phase memory instruction definitions working with new memory model as well. arch/alpha/isa/main.isa: Need to include packet_impl.h for functions that use Packet objects. arch/alpha/isa/mem.isa: Change completeAcc() methods to take Packet object pointers. Also split out StoreCond template for completeAcc(), since that's the only one that needs write_result and we get an unused variable warning if we always have it in there. build/SConstruct: Update list of recognized CPU model names. configs/test/test.py: Change SimpleCPU to AtomicSimpleCPU. cpu/SConscript: Define sources for new CPU models. Add split memory access methods to CPU model signatures. cpu/cpu_models.py: cpu/static_inst.hh: Define new CPU models. cpu/simple/base.cc: cpu/simple/base.hh: Factor out pieces specific to Atomic or Timing models. mem/bus.cc: Bus needs to be able to route timing packets based on explicit dest so responses can get back to requester. Set dest to Packet::Broadcast to indicate that dest should be derived from address. Also set packet src field based on port from which packet is sent. mem/bus.hh: Set packet src field based on port from which packet is sent. mem/packet.hh: Define Broadcast destination address to indicate that packet should be routed based on address. mem/physical.cc: Set packet dest on response so packet is routed back to requester properly. mem/port.cc: Flag blob packets as Broadcast. python/m5/objects/PhysicalMemory.py: Change default latency to be 1 cycle. --HG-- rename : cpu/simple/cpu.cc => cpu/simple/base.cc rename : cpu/simple/cpu.hh => cpu/simple/base.hh extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132 --- configs/test/test.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'configs') diff --git a/configs/test/test.py b/configs/test/test.py index 695d84b73..75e832f5e 100644 --- a/configs/test/test.py +++ b/configs/test/test.py @@ -6,7 +6,7 @@ class HelloWorld(AlphaLiveProcess): magicbus = Bus() mem = PhysicalMemory() -cpu = SimpleCPU(workload=HelloWorld(), mem=magicbus) +cpu = AtomicSimpleCPU(workload=HelloWorld(), mem=magicbus) system = System(physmem=mem, cpu=cpu) system.c1 = Connector(side_a=mem, side_b=magicbus) root = Root(system=system) -- cgit v1.2.3