From 37d48eac19b6b2d5f857ff868ec6d1de4ea02536 Mon Sep 17 00:00:00 2001 From: Gabor Dozsa Date: Wed, 5 Jul 2017 10:52:08 +0100 Subject: config: Change mem_range attribute naming in ARM SimpleSystem MemConfig.config() expects memory ranges to be defined in a particular way. This patch changes the naming of the mem_range attribute in SympleSystem to enable use of MemConfig for configuring the memory. Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d Signed-off-by: Gabor Dozsa Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/4200 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- configs/example/arm/devices.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'configs') diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py index f7375cd9a..467d2b919 100644 --- a/configs/example/arm/devices.py +++ b/configs/example/arm/devices.py @@ -209,13 +209,13 @@ class SimpleSystem(LinuxArmSystem): mem_range = self.realview._mem_regions[0] mem_range_size = long(mem_range[1]) - long(mem_range[0]) assert mem_range_size >= long(Addr(mem_size)) - self._mem_range = AddrRange(start=mem_range[0], size=mem_size) + self.mem_ranges = [ AddrRange(start=mem_range[0], size=mem_size) ] self._caches = caches if self._caches: - self.iocache = IOCache(addr_ranges=[self._mem_range]) + self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]]) else: self.dmabridge = Bridge(delay='50ns', - ranges=[self._mem_range]) + ranges=[self.mem_ranges[0]]) self._pci_devices = 0 self._clusters = [] -- cgit v1.2.3