From 6629d9b2bc58a885bfebce1517fd12483497b6e4 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <Steve.Reinhardt@amd.com>
Date: Wed, 16 Jul 2008 11:10:33 -0700
Subject: mem: use single BadAddr responder per system. Previously there was
 one per bus, which caused some coherence problems when more than one decided
 to respond.  Now there is just one on the main memory bus.  The default bus
 responder on all other buses is now the downstream cache's cpu_side port. 
 Caches no longer need to do address range filtering; instead, we just have a
 simple flag to prevent snoops from propagating to the I/O bus.

---
 configs/common/Caches.py   |  1 +
 configs/common/FSConfig.py | 13 +++++++++----
 configs/example/fs.py      |  3 +--
 3 files changed, 11 insertions(+), 6 deletions(-)

(limited to 'configs')

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index f1ea957b5..1c3b089c7 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -50,3 +50,4 @@ class IOCache(BaseCache):
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
+    forward_snoops = False
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 974003005..a9cd24ba3 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -38,6 +38,11 @@ class CowIdeDisk(IdeDisk):
     def childImage(self, ci):
         self.image.child.image_file = ci
 
+class MemBus(Bus):
+    badaddr_responder = BadAddr()
+    default = Self.badaddr_responder.pio
+
+
 def makeLinuxAlphaSystem(mem_mode, mdesc = None):
     class BaseTsunami(Tsunami):
         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
@@ -50,7 +55,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
         mdesc = SysConfig()
     self.readfile = mdesc.script()
     self.iobus = Bus(bus_id=0)
-    self.membus = Bus(bus_id=1)
+    self.membus = MemBus(bus_id=1)
     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
     self.bridge.side_a = self.iobus.port
@@ -90,7 +95,7 @@ def makeSparcSystem(mem_mode, mdesc = None):
         mdesc = SysConfig()
     self.readfile = mdesc.script()
     self.iobus = Bus(bus_id=0)
-    self.membus = Bus(bus_id=1)
+    self.membus = MemBus(bus_id=1)
     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
     self.t1000 = T1000()
     self.t1000.attachOnChipIO(self.membus)
@@ -130,7 +135,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
         mdesc = SysConfig()
     self.readfile = mdesc.script()
     self.iobus = Bus(bus_id=0)
-    self.membus = Bus(bus_id=1)
+    self.membus = MemBus(bus_id=1)
     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
     self.physmem = PhysicalMemory(range = AddrRange('1GB'))
     self.bridge.side_a = self.iobus.port
@@ -170,7 +175,7 @@ def makeX86System(mem_mode, mdesc = None, self = None):
     self.readfile = mdesc.script()
 
     # Physical memory
-    self.membus = Bus(bus_id=1)
+    self.membus = MemBus(bus_id=1)
     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
     self.physmem.port = self.membus.port
 
diff --git a/configs/example/fs.py b/configs/example/fs.py
index c155d0222..c013a97ae 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -126,8 +126,7 @@ test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
 if options.caches:
     test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
     test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
-    test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
-                       cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
+    test_sys.iocache = IOCache(addr_range=AddrRange(0, size='8GB'))
     test_sys.iocache.cpu_side = test_sys.iobus.port
     test_sys.iocache.mem_side = test_sys.membus.port
 
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