From 6fc0094337bc0356c55232c3850fb5fd2dab1f0c Mon Sep 17 00:00:00 2001
From: Mrinmoy Ghosh <mrinmoy.ghosh@arm.com>
Date: Tue, 25 Sep 2012 11:49:41 -0500
Subject: Cache: add a response latency to the caches

In the current caches the hit latency is paid twice on a miss. This patch lets
a configurable response latency be set of the cache for the backward path.
---
 configs/common/Caches.py     | 12 ++++++++----
 configs/common/O3_ARM_v7a.py | 12 ++++++++----
 2 files changed, 16 insertions(+), 8 deletions(-)

(limited to 'configs')

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 0be8001d7..f16a83559 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -31,7 +31,8 @@ from m5.objects import *
 class L1Cache(BaseCache):
     assoc = 2
     block_size = 64
-    latency = '1ns'
+    hit_latency = '1ns'
+    response_latency = '1ns'
     mshrs = 10
     tgts_per_mshr = 20
     is_top_level = True
@@ -39,14 +40,16 @@ class L1Cache(BaseCache):
 class L2Cache(BaseCache):
     assoc = 8
     block_size = 64
-    latency = '10ns'
+    hit_latency = '10ns'
+    response_latency = '10ns'
     mshrs = 20
     tgts_per_mshr = 12
 
 class PageTableWalkerCache(BaseCache):
     assoc = 2
     block_size = 64
-    latency = '1ns'
+    hit_latency = '1ns'
+    response_latency = '1ns'
     mshrs = 10
     size = '1kB'
     tgts_per_mshr = 12
@@ -55,7 +58,8 @@ class PageTableWalkerCache(BaseCache):
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
-    latency = '10ns'
+    hit_latency = '10ns'
+    response_latency = '10ns'
     mshrs = 20
     size = '1kB'
     tgts_per_mshr = 12
diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py
index 68fb0c543..20ef10ebc 100644
--- a/configs/common/O3_ARM_v7a.py
+++ b/configs/common/O3_ARM_v7a.py
@@ -147,7 +147,8 @@ class O3_ARM_v7a_3(DerivO3CPU):
 # Instruction Cache
 # All latencys assume a 1GHz clock rate, with a faster clock they would be faster
 class O3_ARM_v7a_ICache(BaseCache):
-    latency = '1ns'
+    hit_latency = '1ns'
+    response_latency = '1ns'
     block_size = 64
     mshrs = 2
     tgts_per_mshr = 8
@@ -158,7 +159,8 @@ class O3_ARM_v7a_ICache(BaseCache):
 # Data Cache
 # All latencys assume a 1GHz clock rate, with a faster clock they would be faster
 class O3_ARM_v7a_DCache(BaseCache):
-    latency = '2ns'
+    hit_latency = '2ns'
+    response_latency = '2ns'
     block_size = 64
     mshrs = 6
     tgts_per_mshr = 8
@@ -170,7 +172,8 @@ class O3_ARM_v7a_DCache(BaseCache):
 # TLB Cache 
 # Use a cache as a L2 TLB
 class O3_ARM_v7aWalkCache(BaseCache):
-    latency = '4ns'
+    hit_latency = '4ns'
+    response_latency = '4ns'
     block_size = 64
     mshrs = 6
     tgts_per_mshr = 8
@@ -183,7 +186,8 @@ class O3_ARM_v7aWalkCache(BaseCache):
 # L2 Cache
 # All latencys assume a 1GHz clock rate, with a faster clock they would be faster
 class O3_ARM_v7aL2(BaseCache):
-    latency = '12ns'
+    hit_latency = '12ns'
+    response_latency = '12ns'
     block_size = 64
     mshrs = 16
     tgts_per_mshr = 8
-- 
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