From 90dd745ff61df35b5144ae40be7e6f16dfce463c Mon Sep 17 00:00:00 2001 From: Joel Hestness Date: Wed, 12 Sep 2012 21:42:57 -0500 Subject: se.py Ruby: Connect TLB walker ports In order to ensure correct functionality of switch CPUs, the TLB walker ports must be connected to the Ruby system in x86 simulation. This fixes x86 assertion failures that the TLB walker ports are not connected during the CPU switch process. --- configs/example/se.py | 3 +++ 1 file changed, 3 insertions(+) (limited to 'configs') diff --git a/configs/example/se.py b/configs/example/se.py index 887e414ca..b60baf041 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -198,6 +198,9 @@ if options.ruby: # Connect the cpu's cache ports to Ruby system.cpu[i].icache_port = ruby_port.slave system.cpu[i].dcache_port = ruby_port.slave + if buildEnv['TARGET_ISA'] == 'x86': + system.cpu[i].itb.walker.port = ruby_port.slave + system.cpu[i].dtb.walker.port = ruby_port.slave else: system.system_port = system.membus.slave system.physmem.port = system.membus.master -- cgit v1.2.3