From aa329f4757639820f921bf4152c21e79da74c034 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Fri, 9 May 2014 18:58:49 -0400 Subject: config: Bump DRAM sweep bus speed to match DDR4 config This patch bumps the bus clock speed such that the interconnect does not become a bottleneck with a DDR4-2400-x64 DRAM delivering 19.2 GByte/s theoretical max. --- configs/dram/sweep.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'configs') diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py index 5981d59dd..c1ee0ceca 100644 --- a/configs/dram/sweep.py +++ b/configs/dram/sweep.py @@ -67,11 +67,11 @@ if args: # at the moment we stay with the default open-adaptive page policy, # and address mapping -# start with the system itself, using a multi-layer 1 GHz +# start with the system itself, using a multi-layer 1.5 GHz # bus/crossbar, delivering 64 bytes / 5 cycles (one header cycle) -# which amounts to 12.8 GByte/s per layer and thus per port +# which amounts to 19.2 GByte/s per layer and thus per port system = System(membus = NoncoherentBus(width = 16)) -system.clk_domain = SrcClockDomain(clock = '1GHz', +system.clk_domain = SrcClockDomain(clock = '1.5GHz', voltage_domain = VoltageDomain(voltage = '1V')) -- cgit v1.2.3