From b4dab225fdb528569249b93f1ec7527219c35d54 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 10 Oct 2008 03:50:30 -0700
Subject: X86: Split makeLinuxX86System into makeLinuxX86System and
 makeX86System.

---
 configs/common/FSConfig.py | 37 +++++++++++++++++++++++--------------
 1 file changed, 23 insertions(+), 14 deletions(-)

(limited to 'configs')

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 799e72dc8..8e2b0884c 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -159,8 +159,10 @@ def x86IOAddress(port):
     IO_address_space_base = 0x8000000000000000
     return IO_address_space_base + port;
 
-def makeLinuxX86System(mem_mode, mdesc = None):
-    self = LinuxX86System()
+def makeX86System(mem_mode, mdesc = None, self = None):
+    if self == None:
+        self = X86System()
+
     if not mdesc:
         # generic system
         mdesc = SysConfig()
@@ -171,6 +173,25 @@ def makeLinuxX86System(mem_mode, mdesc = None):
     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
     self.physmem.port = self.membus.port
 
+    # North Bridge
+    self.iobus = Bus(bus_id=0)
+    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+    self.bridge.side_a = self.iobus.port
+    self.bridge.side_b = self.membus.port
+
+    # Platform
+    self.pc = PC()
+    self.pc.attachIO(self.iobus)
+
+    self.intrctrl = IntrControl()
+
+
+def makeLinuxX86System(mem_mode, mdesc = None):
+    self = LinuxX86System()
+
+    # Build up a generic x86 system and then specialize it for Linux
+    makeX86System(mem_mode, mdesc, self)
+
     # We assume below that there's at least 1MB of memory. We'll require 2
     # just to avoid corner cases.
     assert(self.physmem.range.second >= 0x200000)
@@ -187,21 +208,9 @@ def makeLinuxX86System(mem_mode, mdesc = None):
                 size = '%dB' % (self.physmem.range.second - 0x100000 - 1),
                 range_type = 1))
 
-    # North Bridge
-    self.iobus = Bus(bus_id=0)
-    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
-    self.bridge.side_a = self.iobus.port
-    self.bridge.side_b = self.membus.port
-
     # Command line
     self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=9608015'
 
-    # Platform
-    self.pc = PC()
-    self.pc.attachIO(self.iobus)
-
-    self.intrctrl = IntrControl()
-
     return self
 
 
-- 
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