From e7e17f92db8b249aaf99eb93a2447937d78270d5 Mon Sep 17 00:00:00 2001 From: Akash Bagdia Date: Mon, 19 Aug 2013 03:52:28 -0400 Subject: power: Add voltage domains to the clock domains This patch adds the notion of voltage domains, and groups clock domains that operate under the same voltage (i.e. power supply) into domains. Each clock domain is required to be associated with a voltage domain, and the latter requires the voltage to be explicitly set. A voltage domain is an independently controllable voltage supply being provided to section of the design. Thus, if you wish to perform dynamic voltage scaling on a CPU, its clock domain should be associated with a separate voltage domain. The current implementation of the voltage domain does not take into consideration cases where there are derived voltage domains running at ratio of native voltage domains, as with the case where there can be on-chip buck/boost (charge pumps) voltage regulation logic. The regression and configuration scripts are updated with a generic voltage domain for the system, and one for the CPUs. --- configs/common/Options.py | 4 ++++ configs/example/fs.py | 23 ++++++++++++++++++++--- configs/example/se.py | 15 +++++++++++++-- 3 files changed, 37 insertions(+), 5 deletions(-) (limited to 'configs') diff --git a/configs/common/Options.py b/configs/common/Options.py index 2fe77aef3..73def510c 100644 --- a/configs/common/Options.py +++ b/configs/common/Options.py @@ -64,6 +64,10 @@ def addCommonOptions(parser): help = "type of cpu to run with") parser.add_option("--checker", action="store_true"); parser.add_option("-n", "--num-cpus", type="int", default=1) + parser.add_option("--sys-voltage", action="store", type="string", + default='1.0V', + help = """Top-level voltage for blocks running at system + power supply""") parser.add_option("--sys-clock", action="store", type="string", default='1GHz', help = """Top-level clock for blocks running at system diff --git a/configs/example/fs.py b/configs/example/fs.py index 037a54b75..ff59ca67d 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -116,11 +116,20 @@ elif buildEnv['TARGET_ISA'] == "arm": else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) +# Create a top-level voltage domain +test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) + # Create a source clock for the system and set the clock period -test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) +test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, + voltage_domain = test_sys.voltage_domain) + +# Create a CPU voltage domain +test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period -test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock) +test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, + voltage_domain = + test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) @@ -182,11 +191,19 @@ if len(bm) == 2: elif buildEnv['TARGET_ISA'] == 'arm': drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) + # Create a top-level voltage domain + drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) + # Create a source clock for the system and set the clock period drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) + # Create a CPU voltage domain + drive_sys.cpu_voltage_domain = VoltageDomain() + # Create a source clock for the CPUs and set the clock period - drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock) + drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, + voltage_domain = + drive_sys.cpu_voltage_domain) drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, cpu_id=0) diff --git a/configs/example/se.py b/configs/example/se.py index 7b577239f..39572cd86 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -159,11 +159,22 @@ np = options.num_cpus system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], physmem = MemClass(range=AddrRange(options.mem_size)), mem_mode = test_mem_mode, - clk_domain = SrcClockDomain(clock = options.sys_clock), cache_line_size = options.cacheline_size) +# Create a top-level voltage domain +system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) + +# Create a source clock for the system and set the clock period +system.clk_domain = SrcClockDomain(clock = options.sys_clock, + voltage_domain = system.voltage_domain) + +# Create a CPU voltage domain +system.cpu_voltage_domain = VoltageDomain() + # Create a separate clock domain for the CPUs -system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock) +system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, + voltage_domain = + system.cpu_voltage_domain) # All cpus belong to a common cpu_clk_domain, therefore running at a common # frequency. -- cgit v1.2.3