From 04745696b6b523c5e90c335298099600d4a14a76 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 20 Aug 2004 14:54:07 -0400 Subject: Check in of new CPU. This checkin works under non-Fullsystem mode, with no caches. SConscript: Added new CPU files to build. arch/alpha/isa_desc: Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed. arch/isa_parser.py: Added new CPU exec method. base/statistics.hh: Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up. base/traceflags.py: Added new CPU trace flags. cpu/static_inst.hh: Changed static inst to use a file that defines the execute functions. --HG-- extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519 --- cpu/base_dyn_inst.cc | 399 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 399 insertions(+) create mode 100644 cpu/base_dyn_inst.cc (limited to 'cpu/base_dyn_inst.cc') diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc new file mode 100644 index 000000000..bd681e1dc --- /dev/null +++ b/cpu/base_dyn_inst.cc @@ -0,0 +1,399 @@ +/* + * Copyright (c) 2001-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BASE_DYN_INST_CC__ +#define __BASE_DYN_INST_CC__ + +#include +#include +#include + +#include "base/cprintf.hh" + +#include "arch/alpha/faults.hh" +#include "cpu/exetrace.hh" +#include "mem/mem_req.hh" + +#include "cpu/base_dyn_inst.hh" +#include "cpu/beta_cpu/alpha_impl.hh" +#include "cpu/beta_cpu/alpha_full_cpu.hh" + +using namespace std; + +#define NOHASH +#ifndef NOHASH + +#include "base/hashmap.hh" + +unsigned int MyHashFunc(const BaseDynInst *addr) +{ + unsigned a = (unsigned)addr; + unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; + + return hash; +} + +typedef m5::hash_map my_hash_t; +my_hash_t thishash; +#endif + +/** This may need to be specific to an implementation. */ +//int BaseDynInst::instcount = 0; + +//int break_inst = -1; + +template +BaseDynInst::BaseDynInst(MachInst machInst, Addr inst_PC, + Addr pred_PC, InstSeqNum seq_num, + FullCPU *cpu) + : staticInst(machInst), traceData(NULL), cpu(cpu), xc(cpu->xcBase()) +{ + effAddr = MemReq::inval_addr; + physEffAddr = MemReq::inval_addr; + + readyRegs = 0; + + seqNum = seq_num; + + specMemWrite = false; + + canIssue = false; + issued = false; + executed = false; + canCommit = false; + squashed = false; + squashedInIQ = false; + + blockingInst = false; + recoverInst = false; + specMode = false; + btbMissed = false; + // Eventually make this a parameter. + threadNumber = 0; + // Also make this a parameter. + specMode = true; + // Also make this a parameter, or perhaps get it from xc or cpu. + asid = 0; + + // Initialize the fault to be unimplemented opcode. + fault = Unimplemented_Opcode_Fault; + + PC = inst_PC; + nextPC = PC + sizeof(MachInst); + predPC = pred_PC; + + // Make sure to have the renamed register entries set to the same + // as the normal register entries. It will allow the IQ to work + // without any modifications. + for (int i = 0; i < staticInst->numDestRegs(); i++) + { + _destRegIdx[i] = staticInst->destRegIdx(i); + } + + for (int i = 0; i < staticInst->numSrcRegs(); i++) + { + _srcRegIdx[i] = staticInst->srcRegIdx(i); + _readySrcRegIdx[i] = 0; + } + + ++instcount; + + DPRINTF(FullCPU, "DynInst: Instruction created. Instcount=%i\n", + instcount); +} + +template +BaseDynInst::BaseDynInst(StaticInstPtr &_staticInst) + : staticInst(_staticInst), traceData(NULL) +{ + effAddr = MemReq::inval_addr; + physEffAddr = MemReq::inval_addr; + + specMemWrite = false; + + blockingInst = false; + recoverInst = false; + specMode = false; + btbMissed = false; + + // Make sure to have the renamed register entries set to the same + // as the normal register entries. It will allow the IQ to work + // without any modifications. + for (int i = 0; i < staticInst->numDestRegs(); i++) + { + _destRegIdx[i] = staticInst->destRegIdx(i); + } + + for (int i = 0; i < staticInst->numSrcRegs(); i++) + { + _srcRegIdx[i] = staticInst->srcRegIdx(i); + } +} + +template +BaseDynInst::~BaseDynInst() +{ +/* + if (specMemWrite) { + // Remove effects of this instruction from speculative memory + xc->spec_mem->erase(effAddr); + } +*/ + --instcount; + DPRINTF(FullCPU, "DynInst: Instruction destroyed. Instcount=%i\n", + instcount); +} + +template +FunctionalMemory * +BaseDynInst::getMemory(void) +{ + return xc->mem; +} +/* +template +IntReg * +BaseDynInst::getIntegerRegs(void) +{ + return (spec_mode ? xc->specIntRegFile : xc->regs.intRegFile); +} +*/ +template +void +BaseDynInst::prefetch(Addr addr, unsigned flags) +{ + // This is the "functional" implementation of prefetch. Not much + // happens here since prefetches don't affect the architectural + // state. + + // Generate a MemReq so we can translate the effective address. + MemReqPtr req = new MemReq(addr, xc, 1, flags); + req->asid = asid; + + // Prefetches never cause faults. + fault = No_Fault; + + // note this is a local, not BaseDynInst::fault + Fault trans_fault = xc->translateDataReadReq(req); + + if (trans_fault == No_Fault && !(req->flags & UNCACHEABLE)) { + // It's a valid address to cacheable space. Record key MemReq + // parameters so we can generate another one just like it for + // the timing access without calling translate() again (which + // might mess up the TLB). + effAddr = req->vaddr; + physEffAddr = req->paddr; + memReqFlags = req->flags; + } else { + // Bogus address (invalid or uncacheable space). Mark it by + // setting the eff_addr to InvalidAddr. + effAddr = physEffAddr = MemReq::inval_addr; + } + + /** + * @todo + * Replace the disjoint functional memory with a unified one and remove + * this hack. + */ +#ifndef FULL_SYSTEM + req->paddr = req->vaddr; +#endif + + if (traceData) { + traceData->setAddr(addr); + } +} + +template +void +BaseDynInst::writeHint(Addr addr, int size, unsigned flags) +{ + // Need to create a MemReq here so we can do a translation. This + // will casue a TLB miss trap if necessary... not sure whether + // that's the best thing to do or not. We don't really need the + // MemReq otherwise, since wh64 has no functional effect. + MemReqPtr req = new MemReq(addr, xc, size, flags); + req->asid = asid; + + fault = xc->translateDataWriteReq(req); + + if (fault == No_Fault && !(req->flags & UNCACHEABLE)) { + // Record key MemReq parameters so we can generate another one + // just like it for the timing access without calling translate() + // again (which might mess up the TLB). + effAddr = req->vaddr; + physEffAddr = req->paddr; + memReqFlags = req->flags; + } else { + // ignore faults & accesses to uncacheable space... treat as no-op + effAddr = physEffAddr = MemReq::inval_addr; + } + + storeSize = size; + storeData = 0; +} + +/** + * @todo Need to find a way to get the cache block size here. + */ +template +Fault +BaseDynInst::copySrcTranslate(Addr src) +{ + MemReqPtr req = new MemReq(src, xc, 64); + req->asid = asid; + + // translate to physical address + Fault fault = xc->translateDataReadReq(req); + + if (fault == No_Fault) { + xc->copySrcAddr = src; + xc->copySrcPhysAddr = req->paddr; + } else { + xc->copySrcAddr = 0; + xc->copySrcPhysAddr = 0; + } + return fault; +} + +/** + * @todo Need to find a way to get the cache block size here. + */ +template +Fault +BaseDynInst::copy(Addr dest) +{ + uint8_t data[64]; + FunctionalMemory *mem = xc->mem; + assert(xc->copySrcPhysAddr || xc->misspeculating()); + MemReqPtr req = new MemReq(dest, xc, 64); + req->asid = asid; + + // translate to physical address + Fault fault = xc->translateDataWriteReq(req); + + if (fault == No_Fault) { + Addr dest_addr = req->paddr; + // Need to read straight from memory since we have more than 8 bytes. + req->paddr = xc->copySrcPhysAddr; + mem->read(req, data); + req->paddr = dest_addr; + mem->write(req, data); + } + return fault; +} + +template +void +BaseDynInst::dump() +{ + cprintf("T%d : %#08d `", threadNumber, PC); + cout << staticInst->disassemble(PC); + cprintf("'\n"); +} + +template +void +BaseDynInst::dump(std::string &outstring) +{ + std::ostringstream s; + s << "T" << threadNumber << " : 0x" << PC << " " + << staticInst->disassemble(PC); + + outstring = s.str(); +} + + +#if 0 +template +Fault +BaseDynInst::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes) +{ + Fault fault; + + // check alignments, even speculative this test should always pass + if ((nbytes & nbytes - 1) != 0 || (addr & nbytes - 1) != 0) { + for (int i = 0; i < nbytes; i++) + ((char *) p)[i] = 0; + + // I added the following because according to the comment above, + // we should never get here. The comment lies +#if 0 + panic("unaligned access. Cycle = %n", curTick); +#endif + return No_Fault; + } + + MemReqPtr req = new MemReq(addr, thread, nbytes); + switch(cmd) { + case Read: + fault = spec_mem->read(req, (uint8_t *)p); + break; + + case Write: + fault = spec_mem->write(req, (uint8_t *)p); + if (fault != No_Fault) + break; + + specMemWrite = true; + storeSize = nbytes; + switch(nbytes) { + case sizeof(uint8_t): + *(uint8_t)&storeData = (uint8_t *)p; + break; + case sizeof(uint16_t): + *(uint16_t)&storeData = (uint16_t *)p; + break; + case sizeof(uint32_t): + *(uint32_t)&storeData = (uint32_t *)p; + break; + case sizeof(uint64_t): + *(uint64_t)&storeData = (uint64_t *)p; + break; + } + break; + + default: + fault = Machine_Check_Fault; + break; + } + + trace_mem(fault, cmd, addr, p, nbytes); + + return fault; +} + +#endif + +int +BaseDynInst::instcount = 0; + +// Forward declaration... +template BaseDynInst; + +#endif // __BASE_DYN_INST_CC__ -- cgit v1.2.3 From e3fb9afa79e37cb8c60a48b9ff3976665c2c7675 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 23 Sep 2004 14:06:03 -0400 Subject: Update to make multiple instruction issue and different latencies work. Also change to ref counted DynInst. SConscript: Add branch predictor, BTB, load store queue, and storesets. arch/isa_parser.py: Specify the template parameter for AlphaDynInst base/traceflags.py: Add load store queue, store set, and mem dependence unit to the list of trace flags. cpu/base_dyn_inst.cc: Change formating, add in debug statement. cpu/base_dyn_inst.hh: Change DynInst to be RefCounted, add flag to clear whether or not this instruction can commit. This is likely to be removed in the future. cpu/beta_cpu/alpha_dyn_inst.cc: AlphaDynInst has been changed to be templated, so now this CC file is just used to force instantiations of AlphaDynInst. cpu/beta_cpu/alpha_dyn_inst.hh: Changed AlphaDynInst to be templated on Impl. Removed some unnecessary functions. cpu/beta_cpu/alpha_full_cpu.cc: AlphaFullCPU has been changed to be templated, so this CC file is now just used to force instantation of AlphaFullCPU. cpu/beta_cpu/alpha_full_cpu.hh: Change AlphaFullCPU to be templated on Impl. cpu/beta_cpu/alpha_impl.hh: Update it to reflect AlphaDynInst and AlphaFullCPU being templated on Impl. Also removed time buffers from here, as they are really a part of the CPU and are thus in the CPU policy now. cpu/beta_cpu/alpha_params.hh: Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't need to specifically declare any parameters that are already in the BaseFullCPU. cpu/beta_cpu/comm.hh: Changed the structure of the time buffer communication structs. Now they include the size of the packet of instructions it is sending. Added some parameters to the backwards communication struct, mainly for squashing. cpu/beta_cpu/commit.hh: Update typenames to reflect change in location of time buffer structs. Update DynInst to DynInstPtr (it is refcounted now). cpu/beta_cpu/commit_impl.hh: Formatting changes mainly. Also sends back proper information on branch mispredicts so that the bpred unit can update itself. Updated behavior for non-speculative instructions (stores, any other non-spec instructions): once they reach the head of the ROB, the ROB signals back to the IQ that it can go ahead and issue the non-speculative instruction. The instruction itself is updated so that commit won't try to commit it again until it is done executing. cpu/beta_cpu/cpu_policy.hh: Added branch prediction unit, mem dependence prediction unit, load store queue. Moved time buffer structs from AlphaSimpleImpl to here. cpu/beta_cpu/decode.hh: Changed typedefs to reflect change in location of time buffer structs and also the change from DynInst to ref counted DynInstPtr. cpu/beta_cpu/decode_impl.hh: Continues to buffer instructions even while unblocking now. Changed how it loops through groups of instructions so it can properly block during the middle of a group of instructions. cpu/beta_cpu/fetch.hh: Changed typedefs to reflect change in location of time buffer structs and the change to ref counted DynInsts. Also added in branch brediction unit. cpu/beta_cpu/fetch_impl.hh: Add in branch prediction. Changed how fetch checks inputs and its current state to make for easier logic. cpu/beta_cpu/free_list.cc: Changed int regs and float regs to logically use one flat namespace. Future change will be moving them to a single scoreboard to conserve space. cpu/beta_cpu/free_list.hh: Mostly debugging statements. Might be removed for performance in future. cpu/beta_cpu/full_cpu.cc: Added in some debugging statements. Updated BaseFullCPU to take a params object. cpu/beta_cpu/full_cpu.hh: Added params class within BaseCPU that other param classes will be able to inherit from. Updated typedefs to reflect change in location of time buffer structs and ref counted DynInst. cpu/beta_cpu/iew.hh: Updated typedefs to reflect change in location of time buffer structs and use of ref counted DynInsts. cpu/beta_cpu/iew_impl.hh: Added in load store queue, updated iew to be able to execute non- speculative instructions, instead of having them execute in commit. cpu/beta_cpu/inst_queue.hh: Updated change to ref counted DynInsts. Changed inst queue to hold non-speculative instructions as well, which are issued only when commit signals backwards that a nonspeculative instruction is at the head of the ROB. cpu/beta_cpu/inst_queue_impl.hh: Updated to allow for non-speculative instructions to be in the inst queue. Also added some debug functions. cpu/beta_cpu/regfile.hh: Added debugging statements, changed formatting. cpu/beta_cpu/rename.hh: Updated typedefs, added some functions to clean up code. cpu/beta_cpu/rename_impl.hh: Moved some code into functions to make it easier to read. cpu/beta_cpu/rename_map.cc: Changed int and float reg behavior to use a single flat namespace. In the future, the rename maps can be combined to a single rename map to save space. cpu/beta_cpu/rename_map.hh: Added destructor. cpu/beta_cpu/rob.hh: Updated it with change from DynInst to ref counted DynInst. cpu/beta_cpu/rob_impl.hh: Formatting, updated to use ref counted DynInst. cpu/static_inst.hh: Updated forward declaration for AlphaDynInst now that it is templated. --HG-- extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3 --- cpu/base_dyn_inst.cc | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) (limited to 'cpu/base_dyn_inst.cc') diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc index bd681e1dc..c527eb08b 100644 --- a/cpu/base_dyn_inst.cc +++ b/cpu/base_dyn_inst.cc @@ -34,6 +34,7 @@ #include #include "base/cprintf.hh" +#include "base/trace.hh" #include "arch/alpha/faults.hh" #include "cpu/exetrace.hh" @@ -67,12 +68,14 @@ my_hash_t thishash; //int break_inst = -1; -template +template BaseDynInst::BaseDynInst(MachInst machInst, Addr inst_PC, Addr pred_PC, InstSeqNum seq_num, FullCPU *cpu) : staticInst(machInst), traceData(NULL), cpu(cpu), xc(cpu->xcBase()) { + DPRINTF(FullCPU, "DynInst: Creating new DynInst.\n"); + effAddr = MemReq::inval_addr; physEffAddr = MemReq::inval_addr; @@ -123,11 +126,13 @@ BaseDynInst::BaseDynInst(MachInst machInst, Addr inst_PC, ++instcount; +// assert(instcount < 50); + DPRINTF(FullCPU, "DynInst: Instruction created. Instcount=%i\n", instcount); } -template +template BaseDynInst::BaseDynInst(StaticInstPtr &_staticInst) : staticInst(_staticInst), traceData(NULL) { @@ -155,7 +160,7 @@ BaseDynInst::BaseDynInst(StaticInstPtr &_staticInst) } } -template +template BaseDynInst::~BaseDynInst() { /* @@ -169,21 +174,21 @@ BaseDynInst::~BaseDynInst() instcount); } -template +template FunctionalMemory * BaseDynInst::getMemory(void) { return xc->mem; } /* -template +template IntReg * BaseDynInst::getIntegerRegs(void) { return (spec_mode ? xc->specIntRegFile : xc->regs.intRegFile); } */ -template +template void BaseDynInst::prefetch(Addr addr, unsigned flags) { @@ -229,7 +234,7 @@ BaseDynInst::prefetch(Addr addr, unsigned flags) } } -template +template void BaseDynInst::writeHint(Addr addr, int size, unsigned flags) { @@ -261,7 +266,7 @@ BaseDynInst::writeHint(Addr addr, int size, unsigned flags) /** * @todo Need to find a way to get the cache block size here. */ -template +template Fault BaseDynInst::copySrcTranslate(Addr src) { @@ -284,7 +289,7 @@ BaseDynInst::copySrcTranslate(Addr src) /** * @todo Need to find a way to get the cache block size here. */ -template +template Fault BaseDynInst::copy(Addr dest) { @@ -308,7 +313,7 @@ BaseDynInst::copy(Addr dest) return fault; } -template +template void BaseDynInst::dump() { @@ -317,7 +322,7 @@ BaseDynInst::dump() cprintf("'\n"); } -template +template void BaseDynInst::dump(std::string &outstring) { @@ -330,7 +335,7 @@ BaseDynInst::dump(std::string &outstring) #if 0 -template +template Fault BaseDynInst::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes) { -- cgit v1.2.3 From 2fb632dbda1b5db9163322541676cef52a55029f Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 21 Oct 2004 18:02:36 -0400 Subject: Check in of various updates to the CPU. Mainly adds in stats, improves branch prediction, and makes memory dependence work properly. SConscript: Added return address stack, tournament predictor. cpu/base_cpu.cc: Added debug break and print statements. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Comment out possibly unneeded variables. cpu/beta_cpu/2bit_local_pred.cc: 2bit predictor no longer speculatively updates itself. cpu/beta_cpu/alpha_dyn_inst.hh: Comment formatting. cpu/beta_cpu/alpha_full_cpu.hh: Formatting cpu/beta_cpu/alpha_full_cpu_builder.cc: Added new parameters for branch predictors, and IQ parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Register stats. cpu/beta_cpu/alpha_params.hh: Added parameters for IQ, branch predictors, and store sets. cpu/beta_cpu/bpred_unit.cc: Removed one class. cpu/beta_cpu/bpred_unit.hh: Add in RAS, stats. Changed branch predictor unit functionality so that it holds a history of past branches so it can update, and also hold a proper history of the RAS so it can be restored on branch mispredicts. cpu/beta_cpu/bpred_unit_impl.hh: Added in stats, history of branches, RAS. Now bpred unit actually modifies the instruction's predicted next PC. cpu/beta_cpu/btb.cc: Add in sanity checks. cpu/beta_cpu/comm.hh: Add in communication where needed, remove it where it's not. cpu/beta_cpu/commit.hh: cpu/beta_cpu/rename.hh: cpu/beta_cpu/rename_impl.hh: Add in stats. cpu/beta_cpu/commit_impl.hh: Stats, update what is sent back on branch mispredict. cpu/beta_cpu/cpu_policy.hh: Change the bpred unit being used. cpu/beta_cpu/decode.hh: cpu/beta_cpu/decode_impl.hh: Stats. cpu/beta_cpu/fetch.hh: Stats, change squash so it can handle squashes from decode differently than squashes from commit. cpu/beta_cpu/fetch_impl.hh: Add in stats. Change how a cache line is fetched. Update to work with caches. Also have separate functions for different behavior if squash is coming from decode vs commit. cpu/beta_cpu/free_list.hh: Remove some old comments. cpu/beta_cpu/full_cpu.cc: cpu/beta_cpu/full_cpu.hh: Added function to remove instructions from back of instruction list until a certain sequence number. cpu/beta_cpu/iew.hh: Stats, separate squashing behavior due to branches vs memory. cpu/beta_cpu/iew_impl.hh: Stats, separate squashing behavior for branches vs memory. cpu/beta_cpu/inst_queue.cc: Debug stuff cpu/beta_cpu/inst_queue.hh: Stats, change how mem dep unit works, debug stuff cpu/beta_cpu/inst_queue_impl.hh: Stats, change how mem dep unit works, debug stuff. Also add in parameters that used to be hardcoded. cpu/beta_cpu/mem_dep_unit.hh: cpu/beta_cpu/mem_dep_unit_impl.hh: Add in stats, change how memory dependence unit works. It now holds the memory instructions that are waiting for their memory dependences to resolve. It provides which instructions are ready directly to the IQ. cpu/beta_cpu/regfile.hh: Fix up sanity checks. cpu/beta_cpu/rename_map.cc: Fix loop variable type. cpu/beta_cpu/rob_impl.hh: Remove intermediate DynInstPtr cpu/beta_cpu/store_set.cc: Add in debugging statements. cpu/beta_cpu/store_set.hh: Reorder function arguments to match the rest of the calls. --HG-- extra : convert_revision : aabf9b1fecd1d743265dfc3b174d6159937c6f44 --- cpu/base_dyn_inst.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'cpu/base_dyn_inst.cc') diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc index c527eb08b..74f6b8a6c 100644 --- a/cpu/base_dyn_inst.cc +++ b/cpu/base_dyn_inst.cc @@ -83,7 +83,7 @@ BaseDynInst::BaseDynInst(MachInst machInst, Addr inst_PC, seqNum = seq_num; - specMemWrite = false; +// specMemWrite = false; canIssue = false; issued = false; @@ -95,7 +95,7 @@ BaseDynInst::BaseDynInst(MachInst machInst, Addr inst_PC, blockingInst = false; recoverInst = false; specMode = false; - btbMissed = false; +// btbMissed = false; // Eventually make this a parameter. threadNumber = 0; // Also make this a parameter. @@ -139,12 +139,12 @@ BaseDynInst::BaseDynInst(StaticInstPtr &_staticInst) effAddr = MemReq::inval_addr; physEffAddr = MemReq::inval_addr; - specMemWrite = false; +// specMemWrite = false; blockingInst = false; recoverInst = false; specMode = false; - btbMissed = false; +// btbMissed = false; // Make sure to have the renamed register entries set to the same // as the normal register entries. It will allow the IQ to work -- cgit v1.2.3 From 5c4714c1a91680a0253f866958a9db80cd8decb2 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 25 Feb 2005 18:00:49 -0500 Subject: Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes. SConscript: Include new files. arch/alpha/isa_desc: Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them. arch/alpha/isa_traits.hh: Add enum for total number of data registers. arch/isa_parser.py: base/traceflags.py: Include new light-weight OoO CPU model. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Changes to abstract more away from the base dyn inst class. cpu/beta_cpu/2bit_local_pred.cc: cpu/beta_cpu/2bit_local_pred.hh: cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Remove redundant SatCounter class. cpu/beta_cpu/alpha_dyn_inst.cc: cpu/beta_cpu/alpha_full_cpu.cc: cpu/beta_cpu/alpha_full_cpu.hh: cpu/beta_cpu/bpred_unit.cc: cpu/beta_cpu/inst_queue.cc: cpu/beta_cpu/mem_dep_unit.cc: cpu/beta_cpu/ras.cc: cpu/beta_cpu/rename_map.cc: cpu/beta_cpu/rename_map.hh: cpu/beta_cpu/rob.cc: Fix for gcc-3.4 cpu/beta_cpu/alpha_dyn_inst.hh: cpu/beta_cpu/alpha_dyn_inst_impl.hh: Fixes for gcc-3.4. Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst. cpu/beta_cpu/alpha_full_cpu_builder.cc: Make params match the current params inherited from BaseCPU. cpu/beta_cpu/alpha_full_cpu_impl.hh: Fixes for gcc-3.4 cpu/beta_cpu/full_cpu.cc: Use new params pointer in BaseCPU. Fix for gcc-3.4. cpu/beta_cpu/full_cpu.hh: Use new params class from BaseCPU. cpu/beta_cpu/iew_impl.hh: Remove unused function. cpu/simple_cpu/simple_cpu.cc: Remove unused global variable. cpu/static_inst.hh: Include OoODynInst for new lightweight OoO CPU --HG-- extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa --- cpu/base_dyn_inst.cc | 121 ++++++++++++++++++++++++--------------------------- 1 file changed, 57 insertions(+), 64 deletions(-) (limited to 'cpu/base_dyn_inst.cc') diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc index 74f6b8a6c..b8424f576 100644 --- a/cpu/base_dyn_inst.cc +++ b/cpu/base_dyn_inst.cc @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __BASE_DYN_INST_CC__ -#define __BASE_DYN_INST_CC__ +#ifndef __CPU_BASE_DYN_INST_CC__ +#define __CPU_BASE_DYN_INST_CC__ #include #include @@ -43,6 +43,8 @@ #include "cpu/base_dyn_inst.hh" #include "cpu/beta_cpu/alpha_impl.hh" #include "cpu/beta_cpu/alpha_full_cpu.hh" +#include "cpu/ooo_cpu/ooo_impl.hh" +#include "cpu/ooo_cpu/ooo_cpu.hh" using namespace std; @@ -74,92 +76,58 @@ BaseDynInst::BaseDynInst(MachInst machInst, Addr inst_PC, FullCPU *cpu) : staticInst(machInst), traceData(NULL), cpu(cpu), xc(cpu->xcBase()) { - DPRINTF(FullCPU, "DynInst: Creating new DynInst.\n"); + seqNum = seq_num; + + PC = inst_PC; + nextPC = PC + sizeof(MachInst); + predPC = pred_PC; + initVars(); +} + +template +BaseDynInst::BaseDynInst(StaticInstPtr &_staticInst) + : staticInst(_staticInst), traceData(NULL) +{ + initVars(); +} + +template +void +BaseDynInst::initVars() +{ effAddr = MemReq::inval_addr; physEffAddr = MemReq::inval_addr; readyRegs = 0; - seqNum = seq_num; - -// specMemWrite = false; - + completed = false; canIssue = false; issued = false; executed = false; canCommit = false; squashed = false; squashedInIQ = false; + eaCalcDone = false; blockingInst = false; recoverInst = false; - specMode = false; -// btbMissed = false; + // Eventually make this a parameter. threadNumber = 0; - // Also make this a parameter. - specMode = true; + // Also make this a parameter, or perhaps get it from xc or cpu. asid = 0; // Initialize the fault to be unimplemented opcode. fault = Unimplemented_Opcode_Fault; - PC = inst_PC; - nextPC = PC + sizeof(MachInst); - predPC = pred_PC; - - // Make sure to have the renamed register entries set to the same - // as the normal register entries. It will allow the IQ to work - // without any modifications. - for (int i = 0; i < staticInst->numDestRegs(); i++) - { - _destRegIdx[i] = staticInst->destRegIdx(i); - } - - for (int i = 0; i < staticInst->numSrcRegs(); i++) - { - _srcRegIdx[i] = staticInst->srcRegIdx(i); - _readySrcRegIdx[i] = 0; - } - ++instcount; -// assert(instcount < 50); - DPRINTF(FullCPU, "DynInst: Instruction created. Instcount=%i\n", instcount); } -template -BaseDynInst::BaseDynInst(StaticInstPtr &_staticInst) - : staticInst(_staticInst), traceData(NULL) -{ - effAddr = MemReq::inval_addr; - physEffAddr = MemReq::inval_addr; - -// specMemWrite = false; - - blockingInst = false; - recoverInst = false; - specMode = false; -// btbMissed = false; - - // Make sure to have the renamed register entries set to the same - // as the normal register entries. It will allow the IQ to work - // without any modifications. - for (int i = 0; i < staticInst->numDestRegs(); i++) - { - _destRegIdx[i] = staticInst->destRegIdx(i); - } - - for (int i = 0; i < staticInst->numSrcRegs(); i++) - { - _srcRegIdx[i] = staticInst->srcRegIdx(i); - } -} - template BaseDynInst::~BaseDynInst() { @@ -173,14 +141,14 @@ BaseDynInst::~BaseDynInst() DPRINTF(FullCPU, "DynInst: Instruction destroyed. Instcount=%i\n", instcount); } - +/* template FunctionalMemory * BaseDynInst::getMemory(void) { return xc->mem; } -/* + template IntReg * BaseDynInst::getIntegerRegs(void) @@ -395,10 +363,35 @@ BaseDynInst::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes) #endif +template +bool +BaseDynInst::eaSrcsReady() +{ + // For now I am assuming that src registers 1..n-1 are the ones that the + // EA calc depends on. (i.e. src reg 0 is the source of the data to be + // stored) + +// StaticInstPtr eaInst = staticInst->eaCompInst(); + + for (int i = 1; i < numSrcRegs(); ++i) + { + if (!_readySrcRegIdx[i]) + return false; + } + + return true; +} + +// Forward declaration... +template class BaseDynInst; +template class BaseDynInst; + +template <> int BaseDynInst::instcount = 0; -// Forward declaration... -template BaseDynInst; +template <> +int +BaseDynInst::instcount = 0; -#endif // __BASE_DYN_INST_CC__ +#endif // __CPU_BASE_DYN_INST_CC__ -- cgit v1.2.3